FPGA based dual microphone speech enhancement

Biswas, Tanmay; Mandal, Sudhindu Bikash; Saha, Debasri; Chakrabarti, Amlan

doi:10.1007/s00542-019-04299-1

Cited by 3 publications

(2 citation statements)

References 15 publications

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“…In order to verify the performance of EEMD-ICA-WTD, six different denoising methods are used as comparison methods. ey are EMD-TD [33], EMD-WTD [34], EEMD-TD [35], EEMD-WTD [36], wavelet soft threshold denoising (WSTD) [37], and multiband spectral subtraction (MBSS) [38]. To verify the universality of the methods, two kinds of porcine acoustic signals with different SNRins are denoised.…”

Section: Comparison With Other Methodsmentioning

confidence: 99%

An Efficient Porcine Acoustic Signal Denoising Technique Based on EEMD‐ICA‐WTD

Zhang

Tian

Banerjee

et al. 2019

Mathematical Problems in Engineering

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Automatic monitoring of group-housed pigs in real time through porcine acoustic signals has played a crucial role in automated farming. In the process of data collection and transmission, acoustic signals are generally interfered with noise. In this paper, an effective porcine acoustic signal denoising technique based on ensemble empirical mode decomposition (EEMD), independent component analysis (ICA), and wavelet threshold denoising (WTD) is proposed. Firstly, the porcine acoustic signal is decomposed into intrinsic mode functions (IMFs) by EEMD. In addition, permutation entropy (PE) is adopted to distinguish noise-dominant IMFs from the IMFs. Secondly, ICA is employed to extract the independent components (ICs) of the noise-dominant IMFs. The correlation coefficients of ICs and the first IMF are calculated to recognize noise ICs. The noise ICs will be removed. Then, WTD is applied to the other ICs. Finally, the porcine acoustic signal is reconstructed by the processed components. Experimental results show that the proposed method can effectively improve the denoising performance of porcine acoustic signal.

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Section: Comparison With Other Methodsmentioning

confidence: 99%

An Efficient Porcine Acoustic Signal Denoising Technique Based on EEMD‐ICA‐WTD

Zhang

Tian

Banerjee

et al. 2019

Mathematical Problems in Engineering

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show abstract

“…The environmental noise remains an open problem in the field‐programmable gate array (FPGA)‐based embedded robust speech recognition system designed through integrating the empirical mode decomposition (EMD) as well as Genetic Algorithm. Thus the speech diagnosis is important to enhance the quality of the speech signal [1, 2]. During real‐time speech enhancement, the diagnosis of robust speech recognition problems can be treated as a mismatch problem [3].…”

Section: Introductionmentioning

confidence: 99%

Real‐time speech enhancement using optimised empirical mode decomposition and non‐local means estimation

Vumanthala¹,

Bikshalu²

2020

IET Computers & Digital Techniques

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Optimization and hardware implementation of noise reduction algorithm for low‐power audio chip

Wang

Lan

et al. 2022

Concurrency and Computation

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In order to improve the voice quality and decrease the power consumption of the audio electronic products, the noise reduction algorithm and its low‐power hardware implementation are studied. Several types of common noise reduction algorithms are analyzed and simulated, and the log‐minimum mean square error algorithm with statistical‐model‐based voice activity detection noise estimator is selected, which can achieve best signal‐to‐noise ratio improvement of 5.56 dB. The ability of the algorithm to track nonstationary noise is analyzed, and the failure of noise reduction caused by an extreme situation is prevented, and the amount of calculation is reduced by multiplex at the algorithm level. In hardware implementation, look‐up tables are used to implement special operations. High‐significant‐bits search is used to simplify the look‐up table to reduce power consumption, and the speed of the search circuit is optimized by parallel design. The exponential integral and exponential operation are combined as one operation with lower precision requirements, leading to lower power consumption. The design presented in this article passed FPGA verification and taped out with a digital hearing aids chip on SMIC 0.13 μm process. The area and the power consumption of the noise reduction module is 0.206 mm2 and 15.3 μW, respectively, which makes the design suitable for low‐power audio chip applications.

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FPGA based dual microphone speech enhancement

Cited by 3 publications

References 15 publications

An Efficient Porcine Acoustic Signal Denoising Technique Based on EEMD‐ICA‐WTD

An Efficient Porcine Acoustic Signal Denoising Technique Based on EEMD‐ICA‐WTD

Real‐time speech enhancement using optimised empirical mode decomposition and non‐local means estimation

Optimization and hardware implementation of noise reduction algorithm for low‐power audio chip

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