FPGA-Based Distributed Computing Microarchitecture for Complex Physical Dynamics Investigation

Abstract

In this paper, we present a distributed computing system, called DCMARK, aimed at solving partial differential equations at the basis of many investigation fields, such as solid state physics, nuclear physics, and plasma physics. This distributed architecture is based on the cellular neural network paradigm, which allows us to divide the differential equation system solving into many parallel integration operations to be executed by a custom multiprocessor system. We push the number of processors to the limit of one processor for each equation. In order to test the present idea, we choose to implement DCMARK on a single FPGA, designing the single processor in order to minimize its hardware requirements and to obtain a large number of easily interconnected processors. This approach is particularly suited to study the properties of 1-, 2- and 3-D locally interconnected dynamical systems. In order to test the computing platform, we implement a 200 cells, Korteweg-de Vries (KdV) equation solver and perform a comparison between simulations conducted on a high performance PC and on our system. Since our distributed architecture takes a constant computing time to solve the equation system, independently of the number of dynamical elements (cells) of the CNN array, it allows us to reduce the elaboration time more than other similar systems in the literature. To ensure a high level of reconfigurability, we design a compact system on programmable chip managed by a softcore processor, which controls the fast data/control communication between our system and a PC Host. An intuitively graphical user interface allows us to change the calculation parameters and plot the results.

Simulation, Modeling, and Analysis of Soliton Waves Interaction and Propagation in CNN Transmission Lines for Innovative Data Communication and Processing

“…This soliton has a velocity of propagation of 4 according to (9), completing a single loop in about 1250 iterations or rather 12.5 s. There are not any numerical instability or divergence problems during simulations. This simulation allows verifying the quality of Forward Euler method to be used for implementation of soliton ring line on embedded devices [26,33]. As shown in Figure 9, the narrow parallel lines with slope of 4 represent the single soliton which performs loops through the ring.…”

“…So, it was very important to understand the minimum number of processors to implement on FPGA in order to minimize these problems. In addition, implementing a Forward Euler method for numerical integration permits saving a lot of FPGA resources guaranteeing the possibility to implement larger and larger Cellular Neural Network on the FPGA [26], allowing facing more complex dynamics problems.…”

“…Recent works present a completely different approach [23][24][25][26], based on a Cellular Neural Network (CNN). Introduced in 1988 by Chua and Yang [27,28], CNN consists of a lattice of individual cells, which interact with neighboring cells, usually to perform very advanced sensory recognition tasks.…”

Comparative Analysis of Reconfigurable Platforms for Memristor Emulation

“…Moreover, recent trends in hardware design have seen a strong increase in the use of programmable devices [39], such as CPLDs and FPGAs [40,41], and more recently, field programmable analog arrays (FPAA) [42]. Programmable devices can provide flexible and efficient platforms.…”

Architecture Analysis of an FPGA-Based Hopfield Neural Network

“…Other relevant reasons to choose FPGA, reported in the literature, include high performance requirement which is obtained with parallel processing on hardware systems when compared to sequential processing in software implementations [8], reduction of power consumption in robotics or general embedded applications [9], and the maintenance of the flexibility of software simulations while prototyping. In this particular feature, FPGA presents advantages over ASIC neurocomputers because of the decreased hardware cost and circuit development period.…”