FPGA-based digital overcurrent relay with concurrent sense-process-communicate cycles

Integration of wind turbines in distribution systems and development of an adaptive overcurrent relay coordination scheme with considerations for wind speed forecast uncertainty

“…This algorithm is embedded in a central control unit and all the data transfer and system monitoring actions are feasible under the concept of a smart grid. For example, the platform proposed in [21] which consists of FPGA‐based digital overcurrent relays, which conform to IEEE standard C37.112‐1996 and are capable of having the concurrent sensing–processing–communicating, along with a local area network, can be used for communicating relays setting parameters from the central control unit to the relays. Also, a data storage capacity in the central control unit has to be provided by the DS operator to store all the setting parameters calculated in Steps 1 and 2 of the AORCS.…”

Design, Modeling and Implementation of Multi-Function Protective Relay with Digital Logic Algorithm

“…Finite Fourier transform is used for filtering to avoid false tripping in the circuit breaker. The status of the current is also processed and communicated to central control station [2]. FPGA based over current relay, phase loss and locked rotor is simulated and implemented in Xilinx XC4020 FPGA [3].…”

Prototyping and hardware‐in‐loop verification of OCR

“…However, this design does not report extraction of the fundamental frequency component. Another FPGA-based digital OCR is presented in [15]. Here, the pipeline architecture has been used for the design, which was implemented on the Xilinx Virtex-II development board.…”

“…It is evident from the literature reporting FPGA-based replays [13][14][15][16] that each of the designs has its own limitation, which have been removed in the proposed design. Ahuja and Balasubramanian [13] use a preloaded lookup table (LUT) for determination of tripping time with respect to operating current and cannot be used under varying operating current.…”

“…Ahuja and Balasubramanian [13] use a preloaded lookup table (LUT) for determination of tripping time with respect to operating current and cannot be used under varying operating current. Kumar et al [14] and Maheshwari et al [15] lack the verification in the form of FPGA implementation under real-time operating conditions. Wang and Dinavahi [16] have high resource utilisation.…”