FPGA based cellular neural network optimization

Liu, Zhongyang; Luo, Shaoheng; Xu, Xiaowei; Shi, Yiyu; Zhuo, Cheng

doi:10.1145/3183584.3183619

Cited by 2 publications

(2 citation statements)

References 14 publications

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“…The shared data are transferred from one computation unit to the next in a chain mode. Liu et al 27 adopted the similar design. The above accelerators can only accelerate specific neural networks, which is lack of versatility.…”

Section: Related Workmentioning

confidence: 99%

“…Studies 20–22 design the computation units with different data precision and works 23,24 improve the frequency of Digital Signal Processing (DSP) units. Researchers 25–27 accelerate the inference of Convolution Neural Network (CNN) by improving the parallelism of computation and dataflow. Studies 28–31 explore deploying DNN accelerators on one or more FPGAs with system optimization.…”

Section: Introductionmentioning

confidence: 99%

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Field programmable gate array‐based all‐layer accelerator with quantization neural networks for sustainable cyber‐physical systems

2020

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Summary Low‐Bit Neural Network (LBNN) is a promising technique to enrich intelligent applications running on sustainable Cyber‐Physical Systems (CPS). Although LBNN has the advantages of low memory usage, fast inference and low power consumption, Low‐bit design requires additional computation units and may cause large accuracy drop. In this paper, we approach to design Field Programmable Gate Array (FPGA)‐based LBNN accelerator to support sustainable CPS. First, we propose a method to quantize the neural networks into 2‐bit weights, 8‐bit activations and 8‐bit biases with few accuracy loss. The mapping function is presented to approximate discrete space of weights gradually and quantize the activations and biases through the improved straight‐through estimator. Second, we design the bitwise FPGA‐based accelerator to speed up the LBNN. Different from traditional accelerating techniques (mainly focused on convolution layer), the dataflows of fully connected layer, pooling layer and convolution layer are considered to accelerate all layers of neural networks. The 2×8 bitwise multiplier implemented by AND/XOR operation is devised to replace 32×32‐bit multiplication unit, which can bring faster inference and lower power consumption. We conduct extensive experiments on benchmarks of MNIST, CIFAR‐10, CIFAR‐100 and ImageNet to evaluate the efficiency of our approach. The LBNN obtained by our quantization method can save 93.75% memory with 2.26% accuracy loss on average compared with original networks. The FPGA‐based accelerator achieves a peak performance of 427.71 GOPS under 100 MHz working frequency, which outperforms previous approaches significantly.

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Section: Related Workmentioning

confidence: 99%