Field programmable gate array‐based all‐layer accelerator with quantization neural networks for sustainable cyber‐physical systems

Abstract

Summary Low‐Bit Neural Network (LBNN) is a promising technique to enrich intelligent applications running on sustainable Cyber‐Physical Systems (CPS). Although LBNN has the advantages of low memory usage, fast inference and low power consumption, Low‐bit design requires additional computation units and may cause large accuracy drop. In this paper, we approach to design Field Programmable Gate Array (FPGA)‐based LBNN accelerator to support sustainable CPS. First, we propose a method to quantize the neural networks into 2‐bit weights, 8‐bit activations and 8‐bit biases with few accuracy loss. The mapping function is presented to approximate discrete space of weights gradually and quantize the activations and biases through the improved straight‐through estimator. Second, we design the bitwise FPGA‐based accelerator to speed up the LBNN. Different from traditional accelerating techniques (mainly focused on convolution layer), the dataflows of fully connected layer, pooling layer and convolution layer are considered to accelerate all layers of neural networks. The 2×8 bitwise multiplier implemented by AND/XOR operation is devised to replace 32×32‐bit multiplication unit, which can bring faster inference and lower power consumption. We conduct extensive experiments on benchmarks of MNIST, CIFAR‐10, CIFAR‐100 and ImageNet to evaluate the efficiency of our approach. The LBNN obtained by our quantization method can save 93.75% memory with 2.26% accuracy loss on average compared with original networks. The FPGA‐based accelerator achieves a peak performance of 427.71 GOPS under 100 MHz working frequency, which outperforms previous approaches significantly.

Deep Stochastic Logic Gate Networks

“…Our proposed method demonstrated superior performance compared to several state-of-the-art methods, such as Binary Neural Networks, Sparse Neural Networks, and Sparse Function Net, in terms of classification accuracy, except for LowBitNN [55] and SET-MLP [58].…”

“…ReBNet [54], LowBitNN [55] • Sparse Neural Networks for MNIST: Var.Dropout [56], L 0 regularization [57], SET-MLP [58] • Sparse Neural Networks for CIFAR-10: PBW (ResNet32) [59], MLPrune (ResNet32) [60], ProbMask (ResNet32) [61], SET-MLP [58] • Sparse Function Net [62] • Fully-Connected Baselines: Regularized SReLU NN [58], Student-Teacher NN [63] We gathered the comparison results from the deep differentiable logic gate paper [14].…”

“…LowBitNN [55] achieved the best performance among the compared methods on FPGA-based accelerators, utilizing convolutional neural networks with a Support Vector Machine (SVM) classifier. However, their method's reliance on an 8bit activation function and ad-hoc SVM classifier posed draw-backs, as they deviated from the end-to-end neural network learning paradigm.…”

Software and hardware co‐design for sustainable cyber‐physical systems

“…They developed a hybrid optimization framework that maximizes the average accuracy of human activity recognition through energy allocation. Jiang et al 6 designed a field programmable gate array based low‐bit neural network accelerator to support various artificial intelligence applications in sustainable CPS.…”

Iris Image Acquisition and Real-Time Detection System Using Convolutional Neural Network

“…Here, the AlteraCyclone IV series FPGA EP4CE15F17C8N chip can control the whole system. CMOS (Complementary Metal-Oxide-Semiconductor) digital image sensor OV7725 can acquire data, and SDRAM can store data [19]. The structure of the system is shown in figure 1.…”