FPGA assisted design of concatenated LDPC convolutional and BCH codes for optical fiber communications

Cai, Yi; Wang, Weiming; Qian, Weixing; Tao, Kai; Lei, Ming; Yin, Junjie; Zhou, Xia; Zhang, Shihua; Chien, Hung‐Chang

doi:10.1049/cp.2019.0782

Cited by 4 publications

(7 citation statements)

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“…As the 't' bit increases, the chip area and Power of the BCH designs will also increase. The BCH-ED (15,5,3) for TEC utilizes more clock cycles and Power due to the advanced decoding mechanism. As the 't' bit increases, the Throughput and hardware efficiency will be decreased drastically.…”

Section: Resultsmentioning

confidence: 99%

“…The resource utilization of individual BCH encoders and decoders for SEC, DEC, and TEC are tabulated in Table 2, and the graphical representation is in Figure 9. The BCH encoder (15,11,1) utilizes slices of 10 and operates at 605.18 MHz with a combinational delay of 0.729 ns. The BCH encoder (15, 7, 2) utilizes slices of 14 and operates at 866.927 MHz with a delay of 0.756 ns.…”

Section: Resultsmentioning

confidence: 99%

“…The BCH encoder (15, 7, 2) utilizes slices of 14 and operates at 866.927 MHz with a delay of 0.756 ns. The BCH encoder (15,5,3) utilizes slices of 16 and operates at 866.927 MHz with a delay of 0.771 ns. In contrast, the BCH decoder (15,11,1) The performance comparison of the proposed BCH ED with existing BCH approaches is tabulated in Table 3.…”

Section: Resultsmentioning

confidence: 99%

“…Mandal et al [11] present the BCH codes with single-bit correction for Redox-based Random access memory (ReRAM) computation. The BCH codes of (15,11) are incorporated in ReRAM for decoding operation. The BCH module uses 251 and 230 clock cycles to complete encoding and decoding operations.…”

Section: Introductionmentioning

confidence: 99%

“…The BCH decoder works with a throughput of 2.11 Gbps and 4.63 Gbps on Kintex-7 FPGA and ASIC 45-nm Technology, respectively. Cai et al [15] describe the Concatenated LDPC with BCH codes for optical fiber communications. The LDPC-based convolutional codes (CC) offer a throughput of up to 150 Gbps.…”

Section: Introductionmentioning

confidence: 99%

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An efficient high throughput BCH module for multi-bits error correction mechanism on hardware platform

Puttaraju,

Muniyappa

2024

IJEECS

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The bose-chaudhuri-hocquenghem (BCH) codes are a cyclic error correction codes (ECC) class. The BCH is constructed by using a polynomial over the Galois field. The BCH codes can detect and correct the multi-bits with an easy decoding mechanism. The BCH codes are used in most of the storage device's cryptography, disk drives, and satellite applications. This manuscript presents an efficient high-throughput BCH module with an encoding and decoding mechanism for multi-bit corrections. The BCH code of (15, k) is used to construct the encoder and decoder architectures. The BCH encoder decoder (ED) module with single error correction (SEC), double error correction (DEC), and triple-error correction (TEC) are discussed in detail. The BCH encoder module uses a linear feedback shift register (LFSR). The BCH decoder with SEC and DEC is constructed using the syndrome generator module (SGM) and chien search module (CSM). The BCH decoder with TEC is designed using SGM, inversion-based berlekamp-massey-algorithm (BMA), and CSMs. The BCH-ED module with SEC, DEC, and TEC utilizes <1 % chip area on Artix-7 FPGA. The BCH-ED with SEC, DEC, and TEC achieves a throughput of 7.13 Gbps, 1.2 Gbps, and 0.803 Gbps, respectively. Lastly, the BCH module is compared with existing BCH approaches with better improvement in chip area, frequency, and throughput parameters.

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Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

An efficient high throughput BCH module for multi-bits error correction mechanism on hardware platform

Puttaraju,

Muniyappa

2024

IJEECS

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Design of Polar Turbo Product Codes for Optical Fiber Communications Based on FPGA

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Tao

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2022 Asia Communications and Photonics Conference (ACP)

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Performance Oriented DSP for Flexible Long Haul Coherent Transmission

Torbatian

Lavery

Osman

et al. 2022

J. Lightwave Technol.

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In long haul optical fiber communication networks, whichcan span thousands of kilometers, bandwidth is at a premium due to the relatively low availability of optical fibers when compared with network traffic demands. Therefore, these networks require the highest performance in the physical layer, with transceivers that are capable of extracting all the available capacity from each optical fiber. Digital coherent transmitters and receivers, which enhance optical transmission systems by using digital signal processing, are essential for achieving this goal. This tutorial discusses the digital signal processing techniques that are used in the design of high performance coherent modems to compensate for adverse channel effects such as fiber impairments and optoelectronic device nonidealities.

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FPGA assisted design of concatenated LDPC convolutional and BCH codes for optical fiber communications

Cited by 4 publications

References 0 publications

An efficient high throughput BCH module for multi-bits error correction mechanism on hardware platform

An efficient high throughput BCH module for multi-bits error correction mechanism on hardware platform

Design of Polar Turbo Product Codes for Optical Fiber Communications Based on FPGA

Performance Oriented DSP for Flexible Long Haul Coherent Transmission

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