FPGA Architecture: Survey and Challenges

Abstract

Field-Programmable Gate Arrays (FPGAs) have become one of the key digital circuit implementation media over the last decade. A crucial part of their creation lies in their architecture, which governs the nature of their programmable logic functionality and their programmable interconnect. FPGA architecture has a dramatic effect on the quality of the final device's speed performance, area efficiency, and power consumption. This survey reviews the historical development of programmable logic devices, the fundamental programming technologies that the programmability is built on, and then describes the basic understandings gleaned from research on architectures. We include a survey of the key elements of modern commercial FPGA architecture, and look toward future trends in the field. Programming Technologies Every FPGA relies on an underlying programming technology that is used to control the programmable switches that give FPGAs their programmability. There are a number of programming technologies and their differences have a significant effect on programmable logic architecture. The approaches that have been used historically include EPROM [81], EEPROM [68, 174], flash [92], static memory [49], and anti-fuses [38, 93]. Of these approaches, only the flash, static memory and anti-fuse approaches are widely used in modern FPGAs. This survey focuses primarily on static memory-based FPGAs but, in this section, all these modern programming technologies will be reviewed to provide a more complete understanding of the advantages and disadvantages of static memory-based programming.

Inter-FPGA interconnect topologies exploration for multi-FPGA systems

“…In the second variant, two terminal cut-nets are routed through switch box whereas multi terminal cut-nets are routed through direct connections. The main objective to use the switch based routing is to give the flexibility to the routing interconnect because switch-based reconfigurable communication networks have reported to produce good routing results while requiring small area [30]. Six topologies described above are explored using a back-end prototyping flow.…”

“…Instead of using direct two-or multi point tracks for interconnect between different FPGAs of the board, this topology uses a configurable switch for the interconnect. The switch used for the interconnect is a partial cross bar and it uses disjoint [30] connection pattern. This topology is also generic in nature as the switch box used for FPGA interconnect is pre-fabricated.…”

Model‐driven physical‐design automation for FPGAs: fast prototyping and legacy reuse

“…The FPGA is a flexible computing architecture that bridges the gap between application specific integrated circuits (ASIC) and general purpose processors by providing a customizable hardware fabric capable of implementing a wide range of applications. FPGA designs trade the performance of ASICs for flexibility and fabrication costs .…”

FPGA Implementation of 3 bits BCH Error Correcting Codes

“…Field-Programmable Gate Arrays (FPGAs) are pre-fabricated silicon devices that can be electrically programmed to become almost any kind of digital circuit or system [11]. FPGAs provide a number of advantages over fixed-function Application Specific Integrated Circuit (ASIC) technologies such as standard cells.…”

“…FPGAs provide a number of advantages over fixed-function Application Specific Integrated Circuit (ASIC) technologies such as standard cells. ASICs are designed for specific application , and once manufactured, they cannot be modified, while FPGAs are configured in a relatively short amount of time, and often be reconfigured if a mistake is made [11,12]. An FPGA consists of an array of uncommitted configurable logic blocks (CLBs), programmable interconnects and Input Output blocks (IOBs).…”