2006 IEEE International Conference on Field Programmable Technology 2006
DOI: 10.1109/fpt.2006.270309
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FPGA accelerated tate pairing based cryptosystems over binary fields

Abstract: Though the implementation of the Tate pairing is commonly believed to be computationally more intensive than other cryptographic operations, such as ECC point multiplication, there has been a substantial progress in speeding up the Tate pairing computations. Because of their inherent parallelism, the existing Tate pairing algorithms are very suitable for hardware implementation aimed at achieving a high operation speed. Supersingular elliptic curves over binary fields are good candidates for hardware implement… Show more

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Cited by 30 publications
(36 citation statements)
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References 18 publications
(59 reference statements)
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“…We design and implement Tate pairing using field programmable gate array (FPGA) over binary field GF(2 m ). It is more efficient for hardware implementation over binary field compared with other fields such as cubic field GF(3 m ) [47]. The main arithmetic units needed for the Tate pairing computation include addition, Galois field multiplication, Galois field squaring, and Galois field inversion.…”
Section: Tate Pairingmentioning
confidence: 99%
See 3 more Smart Citations
“…We design and implement Tate pairing using field programmable gate array (FPGA) over binary field GF(2 m ). It is more efficient for hardware implementation over binary field compared with other fields such as cubic field GF(3 m ) [47]. The main arithmetic units needed for the Tate pairing computation include addition, Galois field multiplication, Galois field squaring, and Galois field inversion.…”
Section: Tate Pairingmentioning
confidence: 99%
“…Their implementation can compute the Tate pairing over GF(2 283 ) quickly. The algorithm used for Tate pairing in [47] is different from [24,30]. In our work, we implemented the algorithms used in [30].…”
Section: Contributionmentioning
confidence: 99%
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“…There have been many research studies on software and hardware implementations of pairings. Indeed, pairings have implemented on FPGAs [7,12,23,20,3] and smart cards [22]. On the other hand, side channel attacks (SCAs) reveal secret data on hardware devices by monitoring side channel information such as power consumption and timing [15,16].…”
Section: Introductionmentioning
confidence: 99%