2DM)-based field-effect transistors (FETs) with ultrathin bodies and superior electrostatics have great potential for application in ultra-high-density integrated circuits. [2,3] 2D transition-metal dichalcogenide (TMDC) semiconductors, such as MoS 2 and WSe 2 , with adequate bandgaps maintaining low off-state leakage current (I off ), are promising channel materials for highly scaled transistors. [4] Static random-access memory (SRAM) is a volatile storage technology that requires a constant power supply to store data. Unlike dynamic random-access memory, SRAM does not require periodic refreshing, because the flip-flop-based latching circuit can store data in bistable states. [5,6] SRAM, with its rapid access time and low power consumption, has become indispensable in memory technology. For improved computing performance, central processing units are now equipped with large-capacity cache memory (one type of fast SRAM) to hold copies of data from the main memory blocks and reduce the latency of data access. Because the computing cores constantly access on-chip SRAM caches, improvement in the density, performance, and energy efficiency of SRAM caches is essential for future high-performance computing applications. [7][8][9] A typical SRAM comprises six metal-oxide-semiconductor FETs (MOSFETs), including two pull-up, two pull-down, and two pass-gate MOSFETs. Consequently, SRAM faces the same challenges in maintaining low power consumption, high performance, and strong reliability as MOSFET scaling, resulting from the physical limitation of the silicon channel material. When the silicon thickness scales down to sub-10 nm, rough surface scattering and the large leakage current markedly degrade device performance. [3,10] Hence, 2D semiconductor materials with ultrathin bodies and smooth surfaces are potential candidates for replacing silicon at advanced technology nodes (TNs).2DM-based SRAM cells have been studied to generate superior performance. The six-transistor (6T) WSe 2 -based SRAM cells have been demonstrated to operate at a low supply voltage (V dd ) of 0.8 V. [11] Furthermore, the two-transistor two-resistor MoS 2 -based SRAM cells exhibit lower power consumption and higher write stability than the 6T WSe 2 -based SRAM cells. [12] In addition, layered and monolithic 3D integrated 2DM SRAM cells have superior area efficiency and adequate stability. [13,14] This study provides insight into designing high-performance 2D transition-metal dichalcogenide semiconductors, such as MoS 2 and WSe 2 , with adequate bandgaps are promising channel materials for ultrascaled logic transistors. This scalability study of 2D material (2DM)-based field-effect transistor (FET) and static random-access memory (SRAM) cells analyzing the impact of layer thickness reveals that the monolayer 2DM FET with superior electrostatics is beneficial for its ability to mitigate the read-write conflict in an SRAM cell at scaled technology nodes (1-2.1 nm). Moreover, the monolayer 2DM SRAM exhibits lower cell read access time and write time th...