Formation of HfSiON/SiO/sub 2//Si-substrate gate stack with low leakage current for high-performance high-/spl kappa/ MISFETs

Yamaguchi, Masaomi; Sakoda, T.; Minakata, H.; Xiao, Shiqin; Morisaki, Yasuhiro; Ikeda, Keiji; Mishima, Y.

doi:10.1109/ted.2006.870425

Cited by 12 publications

(8 citation statements)

References 6 publications

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“…Furthermore, from Fig. 3 (b), the leakage current at V FB -1 V was decreased from 8.7 to 1.3 A/cm 2 which is compatible value for HfSiON thin film by shortening an annealing duration from 60 to 15 s [13]. It can be said that suppression of local projection formation by shortening annealing duration resulted in the improvement of interface properties.…”

Section: Resultssupporting

confidence: 60%

Selective etching of HfN gate electrode for HfN/HfSiON gate stack in-situ formations

Sano

Ohmi

2011

IEICE Electron. Express

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Abstract:In order to fabricate metal gate/high-k gate stacks utilizing ECR sputtering, selective etching of HfN gate electrodes was investigated. It was found that etching rates of HfN gate electrodes at room temperature were 2.9 and 0.23 nm/s for DHF (1%) and the mixed solution of HF:H 2 O 2 :H 2 O = 1:2:40, respectively. In addition, the etching selectivity for HfN/HfSiON was relatively high, such as the ratio of 65 which was 3 times higher than that of DHF (1%) by the mixed solution. After the in-situ formation of HfN/HfSiON layers on p-Si(100) and post deposition annealing (PDA), pattering of HfN was carried out utilizing the selective etching process. In case the PDA of 800 • C/15 s, the MOS diodes were found to be successfully fabricated, and the equivalent oxide thickness (EOT) of 0.56 nm, and the leakage current at V FB -1 V of 1.3 A/cm 2 were obtained.

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Section: Resultssupporting

confidence: 60%

Selective etching of HfN gate electrode for HfN/HfSiON gate stack in-situ formations

Sano

Ohmi

2011

IEICE Electron. Express

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“…It is about four orders of magnitude lower than SiO 2 with the same EOT, [10,11] as shown in Fig. 5 10 -4 [12] HfSiON/SiO 2 [11] SiO 2…”

Section: Investigation Of Key Processes 31 Hfsion/tan Gate Stack Prmentioning

confidence: 80%

A high performance HfSiON/TaN NMOSFET fabricated using a gate-last process

Xu¹,

Xu²,

Zhou³

et al. 2013

Chinese Phys. B

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A gate-last process for fabricating HfSiON/TaN n-channel metal-oxide-semiconductor-field-effect transistors (NMOSFETs) is presented. In the process, a HfSiON gate dielectric with an equivalent oxide thickness of 10Å was prepared by a simple physical vapor deposition method. Poly-Si was deposited on the HfSiON gate dielectric as a dummy gate. After the source/drain formation, the poly-Si dummy gate was removed by tetramethylammonium hydroxide (TMAH) wet-etching and replaced by a TaN metal gate. Because the metal gate was formed after the ion-implant doping activation process, the effects of the high temperature process on the metal gate were avoided. The fabricated device exhibits good electrical characteristics, including good driving ability and excellent sub-threshold characteristics. The device's gate length is 73 nm, the driving current is 117 µA/µm under power supply voltages of V GS = V DS = 1.5 V and the off-state current is only 4.4 nA/µm. The lower effective work function of TaN on HfSiON gives the device a suitable threshold voltage (∼ 0.24 V) for high performance NMOSFETs. The device's excellent performance indicates that this novel gate-last process is practical for fabricating high performance MOSFETs.

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“…15 Moreover, when manufacturing the multi-layer structure, SiO 2 between high-k material and Si substrate as the interfacial layer (IL) is reported to improve the device performance and the interface quality. 16 It was also reported that the stacking of high-k with SiO 2 at channel interface would be helpful in reducing the barrier-lowering effect due to the high-k fringing fields. 17 Therefore, interfacial layer indeed plays an essential role in high-k devices.…”

Section: Introductionmentioning

confidence: 99%

Photo-induced tunneling currents in MOS structures with various HfO2/SiO2 stacking dielectrics

Pang

Hwu

2014

AIP Advances

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In this study, the current conduction mechanisms of structures with tandem high-k dielectric in illumination are discussed. Samples of Al/SiO2/Si (S), Al/HfO2/SiO2/Si (H), and Al/3HfO2/SiO2/Si (3H) were examined. The significant observation of electron traps of sample H compares to sample S is found under the double bias capacitance-voltage (C-V) measurements in illumination. Moreover, the photo absorption sensitivity of sample H is higher than S due to the formation of HfO2 dielectric layer, which leads to larger numbers of carriers crowded through the sweep of VG before the domination of tunneling current. Additionally, the HfO2 dielectric layer would block the electrons passing through oxide from valance band, which would result in less electron-hole (e−-h+) pairs recombination effect. Also, it was found that both of the samples S and H show perimeter dependency of positive bias currents due to strong fringing field effect in dark and illumination; while sample 3H shows area dependency of positive bias currents in strong illumination. The non-uniform tunneling current through thin dielectric and through HfO2 stacking layers are importance to MOS(p) tunneling photo diodes.

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Formation of HfSiON/SiO/sub 2//Si-substrate gate stack with low leakage current for high-performance high-/spl kappa/ MISFETs

Cited by 12 publications

References 6 publications

Selective etching of HfN gate electrode for HfN/HfSiON gate stack in-situ formations

Selective etching of HfN gate electrode for HfN/HfSiON gate stack in-situ formations

A high performance HfSiON/TaN NMOSFET fabricated using a gate-last process

Photo-induced tunneling currents in MOS structures with various HfO2/SiO2 stacking dielectrics

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