Formation of cobalt silicide spikes in 0.18 μm complementary metal oxide semiconductor process

Abstract

Articles you may be interested inSelf-aligned silicides for Ohmic contacts in complementary metal-oxide-semiconductor technology: TiSi 2 , CoSi 2 , and NiSi J. Vac. Sci. Technol. A 22, 1361 (2004); 10.1116/1.1688364 Low-temperature formation of highly reliable silicon-nitride gate dielectrics with suppressed soft-breakdown phenomena for advanced complementary metal-oxide-semiconductor technology Chemical mechanical polishing of shallow trench isolation using the ceria-based high selectivity slurry for sub-0.18 μm complementary metal-oxide-semiconductor fabrication J. Vac. Sci. Technol. B 20, 918 (2002); 10.1116/1.1475984 Soft-breakdown-suppressed ultrathin atomic-layer-deposited silicon-nitride/SiO 2 stack gate dielectrics for advanced complementary metal-oxide-semiconductor technology Germanium etching in high density plasmas for 0.18 μm complementary metal-oxide-semiconductor gate patterning applications

Surface Cleanness Dependence of the Interfacial Orientation of Endotaxial NiSi[sub 2] on Si(001)

“…It has been reported that the residual oxide between the metal film and a Si substrate can lead to the formation of the twinned boundary on the silicide/Si interface. 17 Thus, the residual oxide on the surface should be the main cause for the formation of the structures with the twinned interface ͑B-type interface͒. The relative amount of the residual oxide determined the possible density of the twinned interface.…”

Microstructure evolution of the Ir-inserted Ni silicides with additional annealing

“…Silicide is an intermetallic compound that is formed between silicon and a transition metal at a stoichiometric composition, and is generally used in the CMOS process within a minimum line width of < 0.25 μm through the salicide process [2]. The silicides that form selectively on the top of the polysilicon gate, source, and the drain provide ohmic contact with silicon, and act as a diffusion barrier between the Si surface and the metal interconnects [3][4][5]. Recently, there has been increasing demand for nano-thick silicides < 50 nm in thickness with good thermal stability and uniformity, e.g.…”

Microstructure evolution with RTA temperature in nano-thick (Ru or Au)-inserted nickel silicides

“…It is formed selectively on the transistor gate and source/drain of CMOS devices to provide ohmic contact with a silicon underlayer, and acts as a diffusion barrier between the upper metal interconnect layer and the silicon [7][8][9]. Such silicide is fabricated using a salicide process, and is used in the CMOS process within a minimum line-width of o0.25 mm [10,11].…”