Formal verification using bounded model checking: SAT versus sequential ATPG engines

Saab, D.G.; Abraham, Jacob A.; Vedula, V.M.

doi:10.1109/icvd.2003.1183144

Cited by 9 publications

(7 citation statements)

References 21 publications

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“…ATPG can be used as an alternative/complement to SAT BMC [1]. It was reported in [14,17] that structural ATPG is competitive in efficiency and capacity for simple properties. Qiang [16] proposed a ATPG-based BMC technique for checking nested properties and compared it to SAT-based BMC system using the USB2.0 IP core in [15].…”

Section: Formal Verification Methodsmentioning

confidence: 98%

Reducing verification overhead with RTL slicing

Ou¹,

Saab²,

Qiang

et al. 2007

Proceedings of the 17th ACM Great Lakes Symposium on VLSI

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Design complexity is increasing with every technology generation, causing verification tools to require large amounts of resources. In this paper, we develop a technique to reduce the complexity of verifying digital designs described in a Hardware Description Language (HDL). For a given property to be verified, we derive an HDL executable design slice that is behaviorally equivalent to the original design. The slice is less complex than the original design and requires fewer resources for analysis by a verification tool. The slicer is implemented as a pre-processor to SMV, a SAT-based verification tool, and Formal, an ATPG-based verification tool. Experimental results on the USB2.0 IP core show that RTL slicing reduces both CPU and memory overhead for both SMV and Formal. This reduction allows the verification tools to effectively deal with complex designs.

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Section: Formal Verification Methodsmentioning

confidence: 98%

Reducing verification overhead with RTL slicing

Ou¹,

Saab²,

Qiang

et al. 2007

Proceedings of the 17th ACM Great Lakes Symposium on VLSI

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“…An established method to prove properties on sequential circuits is bounded model checking (BMC) as first introduced in [1], used, e.g., in [8,25]. In BMC a circuit is modelled iteratively for k steps as a combinational circuit.…”

Section: Introductionmentioning

confidence: 99%

SAT-Based Combinational and Sequential Dependency Computation

Soeken

Raiola

Sterin

et al. 2016

Hardware and Software: Verification and Testing

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Abstract. We present an algorithm for computing both functional dependency and unateness of combinational and sequential Boolean functions represented as logic networks. The algorithm uses SAT-based techniques from Combinational Equivalence Checking (CEC) and Automatic Test Pattern Generation (ATPG) to compute the dependency matrix of multi-output Boolean functions. Additionally, the classical dependency definitions are extended to sequential functions and a fast approximation is presented to efficiently yield a sequential dependency matrix. Extensive experiments show the applicability of the methods and the improved robustness compared to existing approaches.

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“…However, despite several advancements in this area, it remains an intractable problem of significant practical importance for the core task of manufacture testing [8,11,21] as well as for design verification [2,5,26,28]. In recent years CNFbased SAT solvers [7,18,19,33] have emerged as a powerful technology for Boolean reasoning in EDA applications [4,15,31].…”

Section: ½ áòøöó ù ø óòmentioning

confidence: 99%

Can SAT be used to improve sequential ATPG methods?

Prasad

Hsiao²,

Jain³

17th International Conference on VLSI Design. Proceedings.

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In this work we investigate the integration of SAT methods into a simulation-based sequential ATPG tool, STRATEGATE [11], with the aim of improving the state-of-the-art in sequential ATPG. We offer a detailed analysis of possible scenarios and algorithms for performing such an integration. Our preliminary investigations show that such hybrid approaches can be very promising. ½ ÁÒØÖÓ Ù Ø ÓÒThe sequential ATPG problem has been widely investigated for over three decades. However, despite several advancements in this area, it remains an intractable problem of significant practical importance for the core task of manufacture testing [8,11,21] as well as for design verification [2,5,26,28]. In recent years CNFbased SAT solvers [7,18,19,33] have emerged as a powerful technology for Boolean reasoning in EDA applications [4,15,31]. In this work we discuss how SAT methods may be applied to the sequential ATPG problem. This research is motivated by the industrial success of multiengine or hybrid methods in areas such as combinational equivalence checking [14,20] and property checking [9]. The key idea here is to use a carefully orchestrated combination of orthogonal core engines such as BDDs, SAT, simulation, circuit-based ATPG etc. to efficiently solve the overall problem, by using each engine to solve a portion of the problem that it is best suited to. This work aims to apply this philosoply to sequential ATPG. Specifically, our final objective is a fine-grained integration of a powerful SAT solver such as Chaff [19] with a state-of-the-art simulationbased sequential ATPG tool such as STRATEGATE [11].STRATEGATE is based on smart simulation-oriented methods, which are incomplete, while modern SAT solvers implement complete algorithms based on branch-and-bound search, enhanced with learning techniques [18]. These algorithmic features are naturally complementary and hence well-suited for being combined into a more powerful reasoning engine. Moreover, SAT methods have been able to make an impact in areas such as combinational ATPG [15,31] and combinational equivalence checking [20,23], which were thought to be the forte of more traditional technologies such as BDDs or network and rule-based branch-and-bound engines. Therefore, we strongly believe that SAT solvers can significantly improve the state-of-the-art in sequential ATPG.The main contribution of this work is the development of methods for combining state-of-the-art simulation-based sequential ATPG algorithms with efficient (deterministic) SAT techniques. Specifically, we identify places in the sequential ATPG flow of STRATEGATE where SAT methods could symbiotically work with and enhance the existing algorithms, formulate appropriate problems in this flow as SAT problems, and experimentally analyse the comparitive performance of the SAT-based formulation and the STRATEGATE algorithms on these problems. However, the proposed ideas can be used to enhance any simulation-based sequential ATPG framework. We would like to emphasize that this work is meant to be a proof of con...

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Formal verification using bounded model checking: SAT versus sequential ATPG engines

Cited by 9 publications

References 21 publications

Reducing verification overhead with RTL slicing

Reducing verification overhead with RTL slicing

SAT-Based Combinational and Sequential Dependency Computation

Can SAT be used to improve sequential ATPG methods?

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