Design verication poses a very practical problem during circuit synthesis. Learning based verication techniques prove to be an attractive option for verifying two circuits with internal gates having simple functional relationships. We present a verication method which employs a learning technique based on symbolic manipulation and which can more eciently learn indirect implications. The method c an also learn some useful functional implications. We also present a framework in which an indirect implication technique is integrated with an OBDD based verication tool. We present highly ecient verication results on some ISCAS circuits as well as on some very hard industrial circuits.
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