Abstract-This paper addresses the problem of equivalence verification of RTL descriptions that implement arithmetic computations (such as ADD, MULT) over bit-vectors with finite widths. A bit-vector of size m represents integer values from 0 to 2 m −1; implying that the corresponding integer values are reduced modulo 2 m (%2 m ). This suggests that bit-vector arithmetic can be efficiently modeled as algebra over finite integer rings, where the bit-vector size (m) dictates the cardinality of the ring (Z2m ). This paper models the arithmetic datapath verification problem as equivalence testing of polynomial functions from Z 2 n 1 × Z 2 n 2 × · · · × Z 2 n d → Z2m . We formulate the equivalence problem f ≡ g into that of proving whether f − g ≡ 0%2 m . Fundamental concepts and results from number, ring and ideal theory are subsequently employed to develop systematic, complete algorithmic procedures to solve the problem. We demonstrate application of the proposed theoretical concepts to high-level (behavioral/RTL) verification of bit-vector arithmetic within practical CAD settings. Using our approach, we verify a set of arithmetic datapaths at RTL where contemporary verification approaches prove to be infeasible.