Formal verification of word-level specifications

Höreth, Stefan; Drechsler, Rolf

doi:10.1145/307418.307447

Cited by 26 publications

(14 citation statements)

References 15 publications

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“…WLDDs are graph-based representations for functions with a Boolean domain and an integer range [5]. Furthermore, Binary Moment Diagrams (BMD), Multiplicative BMD (*BMD) and Kronecker *BMD (K*BMD) provide representations of integer-valued functions defined over bit-vectors and attempt to make the decomposition more efficient in terms of the graph size [7].…”

Section: Related Workmentioning

confidence: 99%

“…The goal of this section is to introduce a graph-based representation called HED [1] for functions with a mixed Boolean and integer domain and an integer range to represent arithmetic operations at a high level of abstraction, while other proposed Word Level Decision Diagrams (WLDDs) [5], [7] are graph-based representations for functions with a Boolean domain and an integer range. In HED, functions to be represented are maintained as a single graph in canonical form.…”

Section: Horner Expansion Diagram (Hed)mentioning

confidence: 99%

“…This has led to a trend away from dynamic approaches and therefore formal equivalence checking methods have become very important to reduce time-to-market as much as possible. Although contemporary verification approaches have proposed different modeling and manipulation methods for each stage of this complete design flow [3]- [5], there is no total and uniform solution to perform equivalence checking of different models in a unified representation. infinite bit-widths, which can be directly represented by HED [1].…”

Section: Introductionmentioning

confidence: 99%

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A Unified Framework for Equivalence Verification of Datapath Oriented Applications

Alizadeh

Fujita

2009

IEICE Trans. Inf. & Syst.

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SUMMARYIn this paper, we introduce a unified framework based on a canonical decision diagram called Horner Expansion Diagram (HED) [1] for the purpose of equivalence checking of datapath oriented hardware designs in various design stages from an algorithmic description to the gatelevel implementation. The HED is not only able to represent and manipulate algorithmic specifications in terms of polynomial expressions with modulo equivalence but also express bit level adder (BLA) description of gate-level implementations. Our HED can support modular arithmetic operations over integer rings of the form Z 2 n . The proposed techniques have successfully been applied to equivalence checking on industrial benchmarks. The experimental results on different applications have shown the significant advantages over existing bit-level and also word-level equivalence checking techniques.

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Section: Related Workmentioning

confidence: 99%

Section: Horner Expansion Diagram (Hed)mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A Unified Framework for Equivalence Verification of Datapath Oriented Applications

Alizadeh

Fujita

2009

IEICE Trans. Inf. & Syst.

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“…A variety of canonical, directed acyclic graph (DAG) representations have been derived for Boolean functions: BDDs [15], *BMDs [16] and their various word-level extensions [17]. However, these are based on variants of bit-level (binary) decomposition principles.…”

Section: A Vlsi-cadmentioning

confidence: 99%

Equivalence Verification of Polynomial Datapaths Using Ideal Membership Testing

Shekhar

Kalla

Enescu³

2007

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-This paper addresses the problem of equivalence verification of RTL descriptions that implement arithmetic computations (such as ADD, MULT) over bit-vectors with finite widths. A bit-vector of size m represents integer values from 0 to 2 m −1; implying that the corresponding integer values are reduced modulo 2 m (%2 m ). This suggests that bit-vector arithmetic can be efficiently modeled as algebra over finite integer rings, where the bit-vector size (m) dictates the cardinality of the ring (Z2m ). This paper models the arithmetic datapath verification problem as equivalence testing of polynomial functions from Z 2 n 1 × Z 2 n 2 × · · · × Z 2 n d → Z2m . We formulate the equivalence problem f ≡ g into that of proving whether f − g ≡ 0%2 m . Fundamental concepts and results from number, ring and ideal theory are subsequently employed to develop systematic, complete algorithmic procedures to solve the problem. We demonstrate application of the proposed theoretical concepts to high-level (behavioral/RTL) verification of bit-vector arithmetic within practical CAD settings. Using our approach, we verify a set of arithmetic datapaths at RTL where contemporary verification approaches prove to be infeasible.

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“…BDDs can represent many practical logic functions compactly, but cannot represent the multiplier function with reasonable size. To represent such functions compactly, the arithmetic transform decision diagram (ACDD) [16], the binary moment diagram (BMD) [2], the multiplicative BMD (*BMD) [2], the Kronecker *BMD (K*BMD) [7], and the Taylor expansion diagram (TED) [3] have been proposed. ACDD and BMD represent a given integer function using the arithmetic transform expansion, while the multi-terminal BDD (MTBDD) [4] represents the function using the Shannon expansion.…”

Section: Introductionmentioning

confidence: 99%