Formal modeling and verification for pre-charge half buffer gates and circuits

Sakib, Ashiq A.; Smith, Scott C.; Srinivasan, Sudarshan K.

doi:10.1109/mwscas.2017.8052974

Cited by 5 publications

(2 citation statements)

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“…Moreover, due to the hysteresis of individual gates, the state space increases almost exponentially for larger circuits, resulting in an infeasible verification time. This issue with scalability was also encountered by [71]. In [71], the authors developed a model-checking based approach to verify QDI combinational PCHB circuits, where the circuits were also modeled as TSs.…”

Section: Significantlymentioning

confidence: 99%

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Evolution of NULL Convention Logic Based Asynchronous Paradigm: An Overview and Outlook

Khodosevych

Sakib

2022

IEEE Access

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The synchronous design paradigm dominates today's semiconductor industry. However, this clocked approach is facing major challenges with today's high-speed, low-power design expectations, using processes with ever-increasing physical level variability. Several clock related issues surface in designs operating at higher frequencies, which make clock management increasingly difficult. Quasi-delay insensitive (QDI) asynchronous (clockless) designs have proved to be effective in circumventing the major limiting factors associated with the clocked designs. NULL Convention Logic (NCL) is one such QDI asynchronous design paradigm, which presents itself as a promising alternative to conventional synchronous circuits and has already found numerous commercial applications due to its low power, robust architecture, and ease of design reuse. This paper presents the evolution of NCL based asynchronous paradigm over the past two decades, primarily focusing on existing fundamental research in NCL design automation, spanning over NCL synthesis, optimization, testing, and verification. The methods are systematically analyzed to determine their limitations and future research directions.

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Section: Significantlymentioning

confidence: 99%

“…This issue with scalability was also encountered by [71]. In [71], the authors developed a model-checking based approach to verify QDI combinational PCHB circuits, where the circuits were also modeled as TSs.…”

Section: Significantlymentioning

confidence: 99%