An Equivalence Verification Methodology for Asynchronous Sleep Convention Logic Circuits

The synchronous design paradigm dominates today's semiconductor industry. However, this clocked approach is facing major challenges with today's high-speed, low-power design expectations, using processes with ever-increasing physical level variability. Several clock related issues surface in designs operating at higher frequencies, which make clock management increasingly difficult. Quasi-delay insensitive (QDI) asynchronous (clockless) designs have proved to be effective in circumventing the major limiting factors associated with the clocked designs. NULL Convention Logic (NCL) is one such QDI asynchronous design paradigm, which presents itself as a promising alternative to conventional synchronous circuits and has already found numerous commercial applications due to its low power, robust architecture, and ease of design reuse. This paper presents the evolution of NCL based asynchronous paradigm over the past two decades, primarily focusing on existing fundamental research in NCL design automation, spanning over NCL synthesis, optimization, testing, and verification. The methods are systematically analyzed to determine their limitations and future research directions.

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“…The method proves to be highly scalable and significantly faster than previous verification methods. A variant of the method was proposed [75].…”

Section: Significantlymentioning

confidence: 99%

Evolution of NULL Convention Logic Based Asynchronous Paradigm: An Overview and Outlook

Khodosevych

Sakib

2022

IEEE Access

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Exploiting Dual-Rail Register Invariants for Equivalence Verification of NCL Circuits

Srinivasan

Smith

2020

2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS)

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Implementation of FinFET Based Static NCL Threshold Gates: An Analysis of Design Choice

Sakib

Akib

Smith

2020

2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS)

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An Equivalence Verification Methodology for Asynchronous Sleep Convention Logic Circuits

Cited by 4 publications

References 16 publications

Evolution of NULL Convention Logic Based Asynchronous Paradigm: An Overview and Outlook

Evolution of NULL Convention Logic Based Asynchronous Paradigm: An Overview and Outlook

Exploiting Dual-Rail Register Invariants for Equivalence Verification of NCL Circuits

Implementation of FinFET Based Static NCL Threshold Gates: An Analysis of Design Choice

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