Formal implementation verification of the bus interface unit for the Alpha 21264 microprocessor

Postsilicon validation methodology for microprocessors

“…16,17 Tests based on the reference checking principle without assuming a fault model have mainly been used in commercial processor validation. [1][2][3][4][5][6][7][8][9][10][11][12][13][14]18 While formal models and techniques have helped in addressing a class of problems like validating finitestate machines of control logic, a large body of informal techniques are routinely employed in achieving satisfactory validation mainly because of the enormity of the validation space of complex microprocessors. 15 A large portion of the postsilicon effort is more relevant to manufacturing than design validation.…”

“…1,3,7,9,11 Many vendors have successfully achieved this goal in spite of the differences in validation methodologies employed, indicating reasonably distinct validation approaches can work out successfully. [1][2][3][4][5][6][7][8][9][10][11][12][13][14] Generally the vendors have used a combination of directed stress tests, randomized generators, and directed random test generators in validation. 9,14 Pseudorandom testing using randomized generators is effective for combinational design.…”

“…Most of the presilicon validation is done either on a register transfer-level (RTL) simulator or an emulator and has been the primary technique successfully used by a number of commercial manufacturers. [1][2][3][4][5][6][7][8][9][10][11][12][13][14] After the first silicon is ready, postsilicon validation is done in a system environment to flush out bugs missed in presilicon validation. Typical reasons for this are the slow simulation speed that prevents running a large number of tests, tests requiring long execution times, testing done close to release in a hasty manner, tests not run in a particular mode, innovations in circuit technology, and so forth.…”

Using combinational verification for sequential circuits

“…Related to our technique, Bischoff et al [2] verify the implementation of the bus interface unit for the Alpha 21264 microprocessor. They compare RTL with gates extracted from a custom transistor netlist.…”

An efficient verification method for a class of multi-phase sequential circuits

“…Their goal was to prove equivalence after retiming only, so the signal pairs are easy to find, but it may not handle circuits after resynthesis. Bischoff [7] presents a method composed of three conservative algorithms. First, the circuit is cut into slices manually, then, on each slice, the algorithms are used from the fastest to the slowest until a proof, or a counter proof, is found.…”