Postsilicon validation methodology for microprocessors

Rotithor, H.G.

doi:10.1109/54.895008

Cited by 27 publications

(10 citation statements)

References 16 publications

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“…SBST is also a potentially effective solution for postsilicon validation. Execution of verification tests in early silicon prototypes is orders of magnitude faster than simulation-based verification tests and this enables designers to apply more comprehensive tests within a limited time period [17]. However, developing testbenches for post-silicon validation is a tedious task since it suffers from limited internal node observability compared to the full signal observability that a pre-silicon, simulationbased environment offers.…”

Section: Sbst Of Single-threaded Processorsmentioning

confidence: 99%

MT-SBST: Self-test optimization in multithreaded multicore architectures

Foutris

Psarakis

Gizopoulos³

et al. 2010

2010 IEEE International Test Conference

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Section: Sbst Of Single-threaded Processorsmentioning

confidence: 99%

MT-SBST: Self-test optimization in multithreaded multicore architectures

Foutris

Psarakis

Gizopoulos³

et al. 2010

2010 IEEE International Test Conference

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“…Tests in the post-silicon domain consists of directed tests checking specific features of the processor, automatically generated random tests, as well as compatibility checks, such as operating system boot-up and tests with legacy software [2,3]. Directed tests demand much engineering effort and are limited to short sequences or basic system activities.…”

Section: Post-silicon Validation and Its Challengesmentioning

confidence: 99%

“…While tests can be run at-speed on the hardware, test generation and simulation constitute the bottleneck in this process, almost reducing it to the performance level of pre-silicon simulation. Consequently, design houses are forced to spend enormous computational resources on test simulation server farms [3]. Nevertheless, verification with randomized programs remains a central component of the post-silicon validation process, since it can expose many unexpected behaviors of the system missed by directed tests.…”

Section: Post-silicon Validation and Its Challengesmentioning

confidence: 99%

Post-silicon debugging for multi-core designs

Bertacco

2010

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)

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Abstract-Escaped errors in released silicon are growing in number due to the increasing complexity of modern processor designs and shrinking production schedules. Worsening the problem are recent trends towards chip multiprocessors (CMPs) with complex and sometimes non-deterministic memory subsystems prone to subtle, devastating bugs. This deteriorating situation is causing a growing portion of the validation effort to shift to post-silicon, when the first few hardware prototypes become available and where validation experiments are run directly on newly manufactured prototype hardware. While post-silicon validation enables much higher raw performance in test execution, it is a much more challenging environment for bug diagnosis and correction. In this work we briefly overview some of the current methodologies used in industry. We then discuss some recent ideas developed in our research group to leverage the performance advantage of postsilicon validation, while sidestepping its limitations of low internal node observability and expensive bug fixing. Finally we present some of today's general trends in post-silicon validation research.

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“…Aggressive technology scaling and extreme chip integration, combined with the compelling requirement to diminish the time-to-market window have rendered modern microprocessors more prone to design bugs than ever [22], [25], [28]. As a result, silicon debug -the process of validating and debugging a new microprocessor design on its first silicon prototype chips -has evolved to a crucial, time-consuming, and labor-demanding step in a microprocessor's development flow.…”

Section: Introductionmentioning

confidence: 99%

Deconfigurable microprocessor architectures for silicon debug acceleration

Foutris

Gizopoulos

Vera

et al. 2013

Proceedings of the 40th Annual International Symposium on Computer Architecture

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The share of silicon debug in the overall microprocessor chips development cycle is rapidly expanding due to the ever growing design complexity and the limited efficiency of pre-silicon validation methods. Massive application of short random test programs on the prototype microprocessor chips is one of the most effective parts of silicon debug. However, a major bottleneck and source of "noise" in this phase is that large numbers of random test programs fail due to the same or similar design bugs. This redundant behavior adds long delays in the debug flow since each failing random program must be separately examined, although it does not usually bring new debug information. The development of effective techniques that detect dominant modes of failure among random programs and triage them into common categories eliminate redundant debug sessions and significantly boost silicon debug.We propose the employment of deconfigurable microprocessor architectures along with self-checking random test programs to reduce the redundant debug sessions and make the triage step of silicon debug more efficient. Several hardware components of high performance microprocessor micro-architectures can be deconfigured while keeping the functional completeness of the design. This is the property we exploit in our silicon debug methodology for the triaging of random test programs. We support our methodology by a hardware mechanism dedicated to silicon debug that groups the failing test programs into categories depending on the microprocessor hardware components that need to be deconfigured for a random test program to be correctly executed. Identical deconfiguration sequences for multiple test programs indicate the existence of redundancy among them and group them together. This grouping significantly reduces the number of failing tests that must be debugged afterwards. Detailed evaluation of the method on an x86 microprocessor demonstrates its efficiency in reducing the debug sessions and thus in accelerating silicon debug.

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Postsilicon validation methodology for microprocessors

Abstract: A proposed methodology targets microarchitectural attributes prioritized based on the importance of validating corner cases. Several test templates cover all the critical attributes.

Cited by 27 publications

References 16 publications

MT-SBST: Self-test optimization in multithreaded multicore architectures

MT-SBST: Self-test optimization in multithreaded multicore architectures

Post-silicon debugging for multi-core designs

Deconfigurable microprocessor architectures for silicon debug acceleration

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