Formal Analysis of the ACE Specification for Cache Coherent Systems-on-Chip

Kriouile, Abdelaziz; Serwe, Wendelin

doi:10.1007/978-3-642-41010-9_8

Cited by 6 publications

(4 citation statements)

References 16 publications

(18 reference statements)

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“…The proposed formalization and validation approach is used by the industry to validate specific networking protocols to deal with complex behaviors that cannot be proven by classical test and simulation approaches [18], [19].…”

Section: Related Workmentioning

confidence: 99%

Formal Modeling and Validation of ReDy Architecture Intended for IoT Applications

Hafdi¹,

Kriouile²

2017

IJIRCST

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-Internet of Things (IoT) faces different architectural challenges to meet the large scale application issues, the heterogeneity, and the self-adaptivity.Many IoT applications require a dynamic construction of the system and should ensure a high degree of reliability. I. INTRODUCTIONInternet of Things (IoT) is the next wave of digital transformation: many objects that surround us will be connected. Sensors, actuators, and computing units will form networks for different applications. Those applications may concern home and personal uses, enterprises uses, public utilities, or transportation. The IoT is already ready for some specific uses as the majority of personal uses and some enterprise uses. Today, different challenges are still open. In particular architectural challenges to meet the large scale application issues, the heterogeneity, and the self-adaptivity of complex systems. A large part of current work of the IoT architecture have been inherited from the wireless sensor networks background [4]. Other architectures should be investigated for different application domains [5]. Many IoT applications require a dynamic construction of the system and should ensure a high degree of reliability. For this end, we propose the ReDy distributed systems for Reliable and Dynamic distributed systems [1]. Those systems are designed using the ReDy architecture. The ReDy architecture is a reusable solution for a large spectrum of distributed systems. Our solution integrates two important requirements that are common to the concerned systems. The first one is to design the system in a highly dynamic environment, i.e, components can continuously join and leave the system network. The second requirement is about fault tolerance. The designed system should have a high resistance to faults, which permit to preserve the overall behavior of the system even in the presence of faulty components. A large family of systems needs to guarantee the above requirements. Besides proposing a common architecture for those systems, our solution gives general rules that should be respected and implemented during the design phase so as to construct reliable and dynamic distributed systems.As application samples we have: large scale wireless sensor networks, deploy and forget networks, self-adaptive systems of systems, critical infrastructure monitoring, smart grid and household metering, autonomous vehicles, heterogeneous systems with interaction between other sub-networks, smart traffic, intelligent transportation and logistics [5].We take the advantage of the formal methods, witch are a particular kind of mathematically based techniques for the specification and verification, to model the ReDy architecture and to validate complicated behaviors. The use of formal method allows us to ensure a good level of reliability and robustness of our proposed design.Formalizing our system using a formal model let us to express the behavior of the system in an unambiguous way: the formal specification expresses a unique semantic. In addition to...

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Section: Related Workmentioning

confidence: 99%

Formal Modeling and Validation of ReDy Architecture Intended for IoT Applications

Hafdi¹,

Kriouile²

2017

IJIRCST

Self Cite

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“…We use an extension of a previously developed formal model [16] (about 3400 lines of LNT code) of an ACE-based SoC 2 , consisting of a cache-coherent interconnect (CCI) connected to a non-cache-coherent Network-on-Chip (NoC). Figure 1 shows the overall architecture of the model in the configuration used in the present paper.…”

Section: Formal Model Of An Amba 4 Ace Based Socmentioning

confidence: 99%

“…This paper is about the application of formal methods to improve the functional verification of a heterogeneous cache-coherent SoC for a commercial settop-box supporting multiple Ultra HD flows on a single chip currently under development at STMicroelectronics. We use an extension of a previously developed system-level formal model of a cache-coherent SoC [16] and take advantage of equivalence checking, model checking, and test generation facilities offered by the CADP toolbox 1 [8].…”

Section: Introductionmentioning

confidence: 99%

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Using a Formal Model to Improve Verification of a Cache-Coherent System-on-Chip

Kriouile

Serwe

2015

Lecture Notes in Computer Science

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International audienceIn this paper we report about a case study on the functional verification of a System-on-Chip (SoC) with a formal system-level model. Our approach improves industrial simulation-based verification techniques in two aspects. First, we suggest to use the formal model to assess the sanity of an interface verification unit. Second, we present a two-step approach to generate clever semi-directed test cases from temporal logic properties: model-based testing tools of the CADP toolbox generate system-level abstract test cases, which are then refined with a commercial Coverage-Directed Test Generation tool into interface-level concrete test cases that can be executed at RTL level. Applied to an AMBA 4 ACE-based cache-coherent SoC, we found that our approach helps in the transition from interface-level to system-level verification, facilitates the validation of system-level properties, and enables early detection of bugs in both the SoC and the commercial test-bench

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From LOTOS to LNT

Garavel

Lang

Serwe

2017

Lecture Notes in Computer Science

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International audienceWe revisit the early publications of Ed Brinksma devoted, on the one hand, to the definition of the formal description technique LOTOS (ISO International Standard 8807:1989) for specifying communication protocols and distributed systems, and, on the other hand, to two proposals (Extended LOTOS and Modular LOTOS) for making LOTOS a simpler and more expressive language. We examine how this scientific agenda has been dealt with during the last decades. We review the successive enhancements of LOTOS that led to the definition of three languages: E-LOTOS (ISO International Standard 15437:2001), then LOTOS NT, and finally LNT. We present the software implementations (compilers and translators) developed for these new languages and report about their use in various application domains

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Formal Analysis of the ACE Specification for Cache Coherent Systems-on-Chip

Cited by 6 publications

References 16 publications

Formal Modeling and Validation of ReDy Architecture Intended for IoT Applications

Formal Modeling and Validation of ReDy Architecture Intended for IoT Applications

Using a Formal Model to Improve Verification of a Cache-Coherent System-on-Chip

From LOTOS to LNT

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