Fluxon interaction in an overdamped Josephson transmission line

A new frequency multiply circuit generating a 20 GHz sampling clock from an external 5 GHz signal for a lowpass sigmadelta modulator was proposed and designed. The multiply circuit was composed of a ladder circuit, a modified Josephson transmission line (JTL) and T-flip flop (T-FF). We confirmed by numerical simulation that the period jitter of SFQ pulse trains generated by the ladder circuit could be reduced to a value small enough to realize 14-bit resolution for 10 MHz bandwidth by utilizing the repulsion effect between SFQ pulses in the modified JTL. The multiply circuit was fabricated by a 2.5 kA cm 2 Nb process, and its correct operation was confirmed.Index Terms-Analog-to-digital converter, frequency multiply circuit, Josephson device, rapid single flux quantum circuit, sigmadelta modulator.

Section: B Sfq Pulse Behaviors In Jtlsupporting

confidence: 81%

Frequency Multiply Circuit for Superconducting A/D Converter

Yoshida¹,

Hirano²,

Suzuki³

et al. 2005

“…The obvious difference is the transient speed, which is related to the characteristic frequency. Therefore, we normalized the clock frequency by the characteristic frequency given in [14] …”

Section: Resultsmentioning

confidence: 99%

Experimental Analysis of the Bias Dependent Sensitivity of a Josephson Comparator

Haddad

Engert

Brandel

et al. 2015

The Josephson comparator is one of the building blocks of superconductor electronics. It is used as a decision element in all analog and digital circuits. For fast high-bandwidth analog-to-digital converters as well as for digital circuits with reduced switching energy its high sensitivity is most important. Thermal noise limits its decision uncertainty. In this work we analyze the influence of the bias current on the gray zone of a Josephson comparator. Circuit simulations are compared against experimental data. The experimental analysis shows a characteristic dependence of the gray zone on the bias current. We can identify a clear minimum value. This point is related to a certain clock frequency. At low frequencies the simulated relationship between the gray zone and the bias current is in very good agreement with experimental results. The comparison confirmed the circuit model and enables to adjust the design to certain applications to realize the best trade-off between clock frequency and grey zone. The article describes the experimental validation procedure and a derived normalized dependency in detail.

“…We demonstrate the large influence of decision jitter limiting the maximum clock frequency of a counter flow shift register. All results scale with the characteristic voltage of the fabrication process and we could estimate the maximum clock frequency of the shift register to be in the order of the estimated maximum speed of digital signal processing in RSFQ circuits [5].…”

Section: Discussionmentioning

confidence: 99%

“…The normalization shows an independent transition width of (5) and the mean transition time is only slightly increasing for higher current densities. If the data arrives far before the clock pulse, we obtain the smallest delay as well as the smallest jitter for the readout pulse.…”

Section: Decision Jitter and Timing Of The Dffmentioning

confidence: 94%

See 1 more Smart Citation

Technology Related Timing Jitter in Superconducting Electronics

Ortlepp

Uhlmann

2007

Digital superconducting systems based on Josephson junctions make generally use of the synchronous timing strategy. Today, one of its most promising applications is the high speed and high dynamic range signal sensing. A digital signal acquisition system should have a high resolution as well as a short sampling interval with a well known and constant time period. Short term clock fluctuations (clock jitter) induced by thermal noise can significantly disturb the system operation due to hazards of timing constraint violations. This uncertainty in the time period is currently a strong limitation for further improvements of fast signal sensing systems based on superconductive electronics.Recently, several theoretical and experimental studies describe the timing jitter in simple circuits, like Josephson transmission lines. In the presented work, we analyse different fabrication technologies for rapid single flux quantum (RSFQ) electronics and predict their timing jitter by the numerical solution of stochastic differential equations. We obtained a very good agreement between our simulation data and recent experimental results.