Floating point division and square root algorithms and implementation in the AMD-K7/sup TM/ microprocessor

Oberman, Stuart F.

doi:10.1109/arith.1999.762835

Cited by 111 publications

(83 citation statements)

References 8 publications

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“…Several floating-point divide and square-root units have been introduced and studied in the literature [24], [25], [19]. There are mainly two categories of implementations in modern architectures: multiplicative (iterative) and subtractive methods.…”

Section: B Architecturementioning

confidence: 99%

Floating Point Architecture Extensions for Optimized Matrix Factorization

Pedram

Gerstlauer

Geijn

2013

2013 IEEE 21st Symposium on Computer Arithmetic

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Abstract-This paper examines the mapping of algorithms encountered when solving dense linear systems and linear leastsquares problems to a custom Linear Algebra Processor. Specifically, the focus is on Cholesky, LU (with partial pivoting), and QR factorizations. As part of the study, we expose the benefits of redesigning floating point units and their surrounding datapaths to support these complicated operations. We show how adding moderate complexity to the architecture greatly alleviates complexities in the algorithm. We study design trade-offs and the effectiveness of architectural modifications to demonstrate that we can improve power and performance efficiency to a level that can otherwise only be expected of full-custom ASIC designs.A feasibility study shows that our extensions to the MAC units can double the speed of required vector-norm operations while reducing energy by 60%. Similarly, up to 20% speedup with 15% savings in energy can be achieved for LU factorization. We show how such efficiency is maintained even in the complex inner kernels of these operations.

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Section: B Architecturementioning

confidence: 99%

Floating Point Architecture Extensions for Optimized Matrix Factorization

Pedram

Gerstlauer

Geijn

2013

2013 IEEE 21st Symposium on Computer Arithmetic

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“…One of the basic approaches is to use lookup tables (LUT) for obtaining an initial value for iterations, which refine the value to higher accuracy [4,5]. The main differences among these kinds of methods are in the size and content of LUT and the used iteration algorithm.…”

Section: Previous Workmentioning

confidence: 99%

“…Naturally, the accuracy is relatively modest, as we have preferred the lowest area instead of high accuracy. The first method in Table 2 was targeted to DP general purpose processor [5]. It required LUTs of sizes 2 10 × 23 and 2 11 × 23 and multiplier for 76 × 76 operands.…”

Section: Compared Implementationsmentioning

confidence: 99%

“…The main differences among these kinds of methods are in the size and content of LUT and the used iteration algorithm. In [5], a large multiplier was used since it was available in the targeted general purpose processor. In [6], savings were obtained by using a m × n multiplier, m ≤ n, and utilizing the fact that less significant bits of intermediate result do not contribute to the accuracy of the final result.…”

Section: Previous Workmentioning

confidence: 99%

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Low-Complexity Inverse Square Root Approximation for Baseband Matrix Operations

Salmela

Burian

Jarvinen

et al. 2011

ISRN Signal Processing

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Baseband functions like channel estimation and symbol detection of sophisticated telecommunications systems require matrix operations, which apply highly nonlinear operations like division or square root. In this paper, a scalable low-complexity approximation method of the inverse square root is developed and applied in Cholesky and QR decompositions. Computation is derived by exploiting the binary representation of the fixedpoint numbers and by substituting the highly nonlinear inverse square root operation with a more implementation appropriate function. Low complexity is obtained since the proposed method does not use large multipliers or look-up tables (LUT). Due to the scalability, the approximation accuracy can be adjusted according to the targeted application. The method is applied also as an accelerating unit of an application-specific instruction-set processor (ASIP) and as a software routine of a conventional DSP. As a result, the method can accelerate any fixed-point system where cost-efficiency and low power consumption are of high importance, and coarse approximation of inverse square root operation is required.

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“…For instance, in the AMD-K7 processor an optimized and simplified reciprocal and square root reciprocal estimate interpolation unit is implemented [6]. The reciprocal estimate provides at least 14.94 bits of accuracy while the square root reciprocal is accurate to at least 15.84 bits.…”

Section: A Newton-raphson Iterationmentioning

confidence: 99%