Floating gate analog implementation of the additive soft-input soft-output decoding algorithm

Mondragon-Torres, Antonio F.; Sánchez-Sinencio, E.

doi:10.1109/iscas.2002.1010931

Cited by 8 publications

(6 citation statements)

References 24 publications

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“…As a concrete example, a typical 0.18-m CMOS logic process has V. For a canonical analog sum-product decoder implemented in this process, with a 100 nA operating current, (11) requires…”

Section: B Supply Voltage In Canonical Circuitsmentioning

confidence: 99%

Low-voltage CMOS circuits for analog iterative decoders

Winstead

Nguyen

Gaudet

et al. 2006

IEEE Trans. Circuits Syst. I

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Iterative decoders, including Turbo decoders, provide near-optimal error protection for various communication channels and storage media. CMOS analog implementations of these decoders offer dramatic savings in complexity and power consumption, compared to digital architectures. Conventional CMOS analog decoders must have supply voltage greater than 1 V. A new low-voltage architecture is proposed which reduces the required supply voltage by at least 0.4 V. It is shown that the low-voltage architecture can be used to implement the general sum-product algorithm. The low-voltage analog architecture is then useful for implementing Turbo and low-density parity check decoders. The low-voltage architecture introduces new requirements for signal normalization, which are discussed. Measured results for two fabricated low-voltage analog decoders are also presented. Index Terms-Analog decoding, iterative decoding, low-density parity check (LDPC) decoder, low voltage, low power, Turbo decoder.

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“…As a concrete example, a typical 0.18-m CMOS logic process has V. For a canonical analog sum-product decoder implemented in this process, with a 100 nA operating current, (11) requires…”

Section: B Supply Voltage In Canonical Circuitsmentioning

confidence: 99%

Low-voltage CMOS circuits for analog iterative decoders

Winstead

Nguyen

Gaudet

et al. 2006

IEEE Trans. Circuits Syst. I

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“…Hagenauer et al [17] and Loeliger et al [18] came up with a similar approach in which they exploited the similarity between the characteristic equations of transistors and the equations required for calculating a posteriori probability (APP) from log-likelihood ratio (LLR) values, bipolar transistors and MOS transistors were adopted for decoding respectively. Mondragon-Torres et al [19] have used multiple-input floating gate CMOS transistors to represent LLR values in voltage levels. This requires a special CMOS fabrication process with multiple gates.…”

Section: Introductionmentioning

confidence: 99%

Hybrid Architecture for OFDM with Optimized Design of Analog Viterbi Decoder

Cyril¹,

Varugheese²

2012

IJCA

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Analog Viterbi Decoder (AVD) is used for decoding of message from the received signal. Very recently mixed signal architecture for OFDM was proposed, that uses FFT processing in the analog domain. In this work, we propose a modified analog Viterbi decoder that performs decoding in analog domain. The proposed analog Viterbi decoder can be used in the mixed signal architecture of OFDM model and hence the proposed architecture is called as Hybrid OFDM architecture. Software reference model of the proposed AVD is developed using Simulink and is verified for its functionality. The Branch Metric Unit (BMU) and the adder unit that forms the subsystems of AVD are optimized for area, power and speed by designing the adders with 24 transistors. The schematic and layout is designed using Virtuoso targeting 130nm technology, the captured design is verified for its functionality using known test vector. A digital Viterbi decoder is also designed with same specifications as that of AVD, and is synthesized using Design Compiler for comparison. From the results obtained it is found that the AVD is 100 time faster, occupies 8 time less are and consumes power less than 86 micro W compared with digital decoder. The proposed AVD is suitable for low power and high speed applications and can be used in Hybrid OFDM architecture.

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“…First analogue implementations of binary decoders were reported in the literature in [3][4][5]. Those implementations reported reductions of 1-3 orders of magnitude in number of required transistors and in consumed energy, and the same order of improvement in processing speed.…”

Section: Introductionmentioning

confidence: 99%

Analogue MIMO Detection

Piechocki

Soler-Garrido

McNamara

et al. 2006

EURASIP J. Adv. Signal Process.

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In this contribution we propose an analogue receiver that can perform turbo detection in MIMO systems. We present the case for a receiver that is built from nonlinear analogue devices, which perform detection in a "free-flow" network (no notion of iterations). This contribution can be viewed as an extension of analogue turbo decoder concepts to include MIMO detection. These first analogue implementations report reductions of few orders of magnitude in the number of required transistors and in consumed energy, and the same order of improvement in processing speed. It is anticipated that such analogue MIMO decoder could bring about the same advantages, when compared to traditional digital implementations.

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Floating gate analog implementation of the additive soft-input soft-output decoding algorithm

Cited by 8 publications

References 24 publications

Low-voltage CMOS circuits for analog iterative decoders

Low-voltage CMOS circuits for analog iterative decoders

Hybrid Architecture for OFDM with Optimized Design of Analog Viterbi Decoder

Analogue MIMO Detection

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