Flip chip underfill reliability of CSP during IR reflow soldering

Ohshima, Y.; Nakazawa, T.; Doi, K.; Aoki, Hideo; Hiruta, Y.

doi:10.1109/relphy.1997.584248

Cited by 15 publications

(4 citation statements)

References 2 publications

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“…Compared with conventional wire-bonding technology, flip-chip has much shorter interconnects, significantly reducing parasitic effects at millimeter-wave frequencies [3]. However, the reliability of flip-chip packaging is critical due to the thermal mechanical stresses from mismatch in the coefficient of thermal expansion (CTE) [4], [5]. Therefore, underfill has been widely applied in the past.…”

Section: Introductionmentioning

confidence: 99%

Investigation of the Flip-Chip Package With BCB Underfill for W-Band Applications

Wang

Hsu

et al. 2014

IEEE Microw. Wireless Compon. Lett.

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Flip-chip package has great potential for use in millimeter-wave applications. However, the coefficient of thermal expansion mismatch between the chip and the substrate usually generates thermal stresses that fracture the flip-chip structure. The use of underfills with low dielectric loss is essential to improve the mechanical strength and reliability of the flip-chip package. Benzocyclobutene (BCB) was used in this study as the underfill material for the flip-chip structure using the no-flow process. The flip-chip structure with BCB injection provides good RF performance with a return loss of better than 18 dB and an insertion loss of 0.6 dB up to 100 GHz, in addition to a lower dielectric loss. Furthermore, thermal cycle and shear force tests show that the underfill injection can significantly improve the reliability of a flip-chip package.

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Section: Introductionmentioning

confidence: 99%

Investigation of the Flip-Chip Package With BCB Underfill for W-Band Applications

Wang

Hsu

et al. 2014

IEEE Microw. Wireless Compon. Lett.

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“…A commercially available PCB (RO3210 organic substrate from Rogers) was adopted for the feasibility study of the proposed technology. To further improve the reliability of the overall structure, an epoxy-based underfill, which can alleviate the stress on the bump transitions between the chips and the PCB, [12][13][14] was applied. Possible performance degradations at high frequen-cies due to the inclusion of the underfill (though with low dielectric constant) were taken care of by the optimal design of the geometries on the RO3210 organic substrate through full-wave electromagnetic simulation.…”

Section: Introductionmentioning

confidence: 99%

Flip-Chip Packaging of Low-Noise Metamorphic High Electron Mobility Transistors on Low-Cost Organic Substrate

Wang

Kuo

Hsu

et al. 2011

Jpn. J. Appl. Phys.

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A 6-dimensional grand unified theory with the compact space having the topology of a real projective plane, i.e., a 2-sphere with opposite points identified, is considered. The space is locally flat except for two conical singularities where the curvature is concentrated. One supersymmetry is preserved in the effective 4d theory. The unified gauge symmetry, for example SU(5) , is broken only by the non-trivial global topology. In contrast to the Hosotani mechanism, no adjoint Wilson-line modulus associated with this breaking appears. Since, locally, SU(5) remains a good symmetry everywhere, no UV-sensitive threshold corrections arise and SU(5)-violating local operators are forbidden. Doublettriplet splitting can be addressed in the context of a 6d N = 2 super Yang-Mills theory with gauge group SU(6). If this symmetry is first broken to SU(5) at a fixed point and then further reduced to the standard model group in the above non-local way, the two light Higgs doublets of the MSSM are predicted by the group-theoretical and geometrical structure of the model.

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“…Sn-Ag solder bump heights were measured by a focus point detection method. For higher reliable CSP packages, bump heights of more than 70 pm as reflowed are necessary [3,4]. The present bump process can easily provide the required bump heights.…”

Section: Figure 2 Cross-sectional Sem View Of the Plating Maskmentioning

confidence: 99%

Eutectic Sn-Ag solder bump process for ULSI flip chip technology

Ezawa¹,

Miyata²,

Honma³

et al.

2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070)

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The novel developed Sn-Ag eutectic solder bump process provides several advantages over conventional solder bump process schemes. Steep wall bumps as plated were fabricated using the nega-type photo resist with a thickness of more than 50pm by one time spin coating. This improves productivity for mass production. The 2-step electroplating process was performed using separate plating reactors for Ag and Sn. The eutectic Sn-Ag alloy bumps were easily obtained by annealing the metal stacks with Sn layer on Ag layer sequentially electroplated. This electroplating process does not need to strict control of the content ratio of Ag to Sn in an alloy plating solution even with increasing electroplating depositions. The novel developed process gives the withinwafer uniformity of the bump height as reflowed of less than 10 % and of the Sn-Ag alloy composition as reflowed of less than ~S w t . ' %~A g , analyzed by ICP spectrometry. Shear strength measurements were performed to know thermal stability for the structure of Cu padsiTi/Ni/Pd/Sn-Ag eutectic solder stack. In the case of the Ti (100nm)/Ni (300nm)Pd (50nm) barrier metal stacks, the shear strength after 5 times annealing in N2 ambience at 260°C decreased to 70% than that as reflowed. As the Ti becomes thicker in the Ti/Ni/'Pd metal stack, shear strengths are improved. Comparing the structure of Cu/Ti/NiPd/Sn-Ag eutectic solder with the case of Ta/Ti/Ni/Pd and Nb/Ti/Ni/Pd barrier metal stacks, the analysis results of Auger spectrometry show that Sn drfision into Cu to form Cu-Sn alloy was observed only in Cu/Ta/Ti/Ni/Pd barrier metal stacks. These results suggest that the same Ti/Ni/Pd barrier metal stack as used in Sn-Pb solder bump and Au bump is viable for ULSIs with Cu interconnects.

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Flip chip underfill reliability of CSP during IR reflow soldering

Cited by 15 publications

References 2 publications

Investigation of the Flip-Chip Package With BCB Underfill for W-Band Applications

Investigation of the Flip-Chip Package With BCB Underfill for W-Band Applications

Flip-Chip Packaging of Low-Noise Metamorphic High Electron Mobility Transistors on Low-Cost Organic Substrate

Eutectic Sn-Ag solder bump process for ULSI flip chip technology

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