FlexWare : A Flexible Firmware Development Environment for Embedded Systems

Paulin, Pierre; Liem, Clifford; May, Trevor; Sutarwala, Shailesh

doi:10.1007/978-1-4615-2323-9_4

Cited by 40 publications

(25 citation statements)

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“…Approaches based on an instruction set/architecture combination are as follows. FlexWare [14] is more related to RTL than to the level of ADLs. The PEAS-III [15] and the derived ASIP-Meister [16] work with a set of predefined components.…”

Section: Related Workmentioning

confidence: 96%

A framework for automated and optimized ASIP implementation supporting multiple hardware description languages

Schliebusch

Chattopadhyay

Kammler

et al. 2005

Proceedings of the 2005 Conference on Asia South Pacific Design Automation - ASP-DAC '05

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Abstract-Architecture Description Languages (ADLs) are widely used to perform design space exploration for Application Specific Instruction Set Processors (ASIPs). While the design space exploration is well supported by numerous tools providing high flexibility and quality, the methodology of automated implementation is limited to simple transformations. Assuming fixed architectural templates, information given in the ADL is directly mapped to a hardware description on Register Transfer Level (RTL). Gate-Level synthesis tools are not able to perform potential optimizations, as the computational complexity grows exponential with the size of the architecture. Information such as exclusiveness, parallelism or boolean relations are spread over multiple modules and therefore hard to determine. In this paper, we present an ASIP synthesis approach from architecture description languages, based on an Intermediate Representation (IR). The IR is the key technology to provide new languageindependent high-level optimizations and to realize different hardware description language backends. The feasibility of our approach is proven in a case-study.

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Section: Related Workmentioning

confidence: 96%

A framework for automated and optimized ASIP implementation supporting multiple hardware description languages

Schliebusch

Chattopadhyay

Kammler

et al. 2005

Proceedings of the 2005 Conference on Asia South Pacific Design Automation - ASP-DAC '05

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“…Retargetable code generation and optimization systems for irregular architectures, mostly digital signal processors are MIMOLA [27], RECORD [25], CBC [11], CHESS [24], Flexware [30], SPAM [38], Express [14], or AVlV [15]. While these systems do not support transforrmtions on assembly-or executable code, SALTO [4] is a retargetable system designed to support implementing tools for analyses and transformations of assembly code.…”

Section: Related Workmentioning

confidence: 99%

Generic software pipelining at the assembly level

Pister

Kastner

2005

Proceedings of the 2005 Workshop on Software and Compilers for Embedded Systems - SCOPES '05

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Software used in embedded systems is subject to strict timing and space constraints. The growing software complexity creates an urgent need for fast program execution under the constraint of very limited code size. However, even modern compilers produce code whose quality often is far away from the optimum. The PROPAN system is a postpass optimization framework that enables high-quality machinedependent postpass optimizers to be generated from a concise hardware specification. The postpass approach allows to enhance the code quality of existing compilers and offers a smooth integration into existing development tool chains. In this article we present an adaptation of the modulo scheduling software pipelining algorithm to the postpass level The implementation is fully retargetable and has been incorporated in the PROPAN system. The differences of postpass modulo scheduling compared to the standard version of the algorithm are outlined. Experimental results conducted on the Philips TriMedia TMI O00 processor demonstrate that modulo scheduling can be applied at the postpass level and allows to achieve a significant code speedup with moderate code size increase.

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“…EXPRESSION [10], LISA [11] and FLEXWARE [12] adapt mixed-level descriptions. EXPRESSION generates a compiler/simulator toolkit automatically.…”

Section: Introductionmentioning

confidence: 99%

Interface Implementation Using Ajax for Web-Based Instruction Set Simulator

Yanagisawa¹,

Uehara

Mori

2008

22nd International Conference on Advanced Information Networking and Applications - Workshops (Aina Workshops 2008)

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SSC-DASH (Server Side C-DASH) has been developed as a web-based HW/SW codesign tool for designing processors. SSC-DASH obtains a processor definition file via web browser and generates a HW (synthesizable Verilog-HDL description) and SWDE (Software Development Environment) for the generated processor. The SWDE includes ISS (Instruction SetSimulator), assembler, disassembler and compiler. For the verification of the defined processor, processor developers have to download the generated SWDE, every time, even where changes are small. To improve the usability of this system a web-based interface for the generated SWDE is implemented using Ajax. Using Ajax, download of the SWDE becomes unnecessary and makes it possible to verify the processor on the server quickly and easily. This greatly improves the usability of the SWDE. In this paper, we describe implementation of web-based ISS using Ajax.

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FlexWare : A Flexible Firmware Development Environment for Embedded Systems

Cited by 40 publications

References 0 publications

A framework for automated and optimized ASIP implementation supporting multiple hardware description languages

A framework for automated and optimized ASIP implementation supporting multiple hardware description languages

Generic software pipelining at the assembly level

Interface Implementation Using Ajax for Web-Based Instruction Set Simulator

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