A framework for automated and optimized ASIP implementation supporting multiple hardware description languages

Abstract

Abstract-Architecture Description Languages (ADLs) are widely used to perform design space exploration for Application Specific Instruction Set Processors (ASIPs). While the design space exploration is well supported by numerous tools providing high flexibility and quality, the methodology of automated implementation is limited to simple transformations. Assuming fixed architectural templates, information given in the ADL is directly mapped to a hardware description on Register Transfer Level (RTL). Gate-Level synthesis tools are not able to perform potential optimizations, as the computational complexity grows exponential with the size of the architecture. Information such as exclusiveness, parallelism or boolean relations are spread over multiple modules and therefore hard to determine. In this paper, we present an ASIP synthesis approach from architecture description languages, based on an Intermediate Representation (IR). The IR is the key technology to provide new languageindependent high-level optimizations and to realize different hardware description language backends. The feasibility of our approach is proven in a case-study.

Integrated video motion estimator with Retinex-like pre-processing for robust motion analysis in automotive scenarios: algorithmic and real-time architecture design

“…design, supported by languages for processor architecture description such as LISAtek [27,28], and synthesis on standard-cell CMOS technologies of an ASIP. As already proved in literature [28][29][30][31][32][33][34][35][36][37][38] for hardware implementation of a specific class of digital signal processing algorithms, including video and image processing as discussed in our previous works [24,25,39], ASIPs offer a better trade-off between flexibility and performance versus classic ASICs and DSPs solutions. By exploiting the ASIPs paradigm the designer can achieve flexibility within an application domain, being able to accomplish a group of functionalities using a set of common operations.…”

ASIP-based reconfigurable architectures for power-efficient and real-time image/video processing

“…Starting from the linearized and bit-true model, the design of the reconfigurable ASIP architecture, detailed in Section 3.3, is addressed using the ADL LISA [10,11].…”

“…In the most recent panorama [1][2][3][4][5][6][7][8][9][10][11][12] of digital processing systems, the design of application specific instruction-set processors (ASIPs) is gaining ground to fill the gap between ASICs and DSPs. ASIPs are flexible within an application domain, being able to accomplish a group of functionalities using a set of common operations.…”

“…Hence, computation intensive tasks can be managed efficiently in real-time but at the same time different programmable versions of the same algorithmic class can be supported. Architecture description languages (ADL) exist [10][11][12] to help the processor designer by automatically generating the software toolsuite (compiler, assembler, linker, simulator) as well as a register transfer level (RTL) VHDL model of the processor with a quality comparable to handwritten code [10][11][12]. The generated RTL model can be synthesized in semicustom CMOS or field programmable gate array (FPGA) technologies or integrated as intellectual property (IP) macrocell in more complex multi processor system-on-chip (SoC) platforms.…”

Algorithmic and architectural design for real-time and power-efficient Retinex image/video processing

“…In the field of digital processing systems ASIPs [26][27][28][29] are gaining ground to fill the gap between ASICs and DSPs. ASIPs are flexible within an application domain, being able to accomplish a group of functionalities using a set of common operations.…”