“FlexTrate ^TM” — Scaled Heterogeneous Integration on Flexible Biocompatible Substrates Using FOWLP

Fukushima, T.; Alam, A. H. M. Zahirul; Wan, Zhe; Jangam, Siva Chandra; Pal, Saptadeep; Ezhilarasu, Goutham; Bajwa, Adeel; Iyer, Subramanian S.

doi:10.1109/ectc.2017.226

Cited by 17 publications

(5 citation statements)

References 4 publications

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“…Multiple power boards are vertically stacked and connected to a common PCB for granular routing to the silicon wafer. This PCB, called power platform PCB, is segmented, embedded in PDMS, a flexible molding compound, and interconnected using the FlexTrate process [40]. Multi-strand power cables from the power board are solder-connected to the power platform PCB.…”

Section: Discussionmentioning

confidence: 99%

“…Nonetheless, static charge accumulation during transport and handling can exceed the limits of a protection network, causing ESD damage [10]. In advanced packaging schemes, bare dies from a variety of sources need to be integrated using advanced methods such as the Silicon Interconnect Fabric technology or fan-out wafer level packaging such as FlexTrate TM [40]. An accurate ESD sensor can allow us to pinpoint at which stage in the supply chain an ESD event has occurred and potentially avoid the assembly of parts that may have been compromised.…”

Section: Introductionmentioning

confidence: 99%

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An On-Chip ESD Sensor for Use in Advanced Packaging

Kannan

Vaisband

Sahoo

et al. 2022

IEEE Trans. Compon., Packag. Manufact. Technol.

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Electrostatic discharge (ESD) in integrated circuits (ICs) occurs due to charge transfer between two components in close proximity with voltage imbalance. As a result of an ESD event, a high transient current (up to few tens of Amps) and large voltage (up to several tens of kV) can develop between the two components. This fast (∼ 150 ns) transient phenomenon can cause serious damage or degrade the performance of affected ICs. ESD results in about 35% of IC field returns and is the cause of several billion dollars loss to the semiconductor industry per year. Even though most modern ICs have on-chip ESD protection circuitry embedded, static charge accumulation during transport and handling may exceed the limits of ESD protection and cause damage to the ICs. Advanced packaging schemes existing today are not amenable to rework if one or more dielets are ESD compromised. An on-chip ESD sensor would help in identifying and preventing the assembly of ESD compromised dielets in any advanced packaging schemes. In this dissertation, two approaches for on-chip ESD detection that can be employed on any die are presented: variable dielectric width capacitor, and vertical MOSCAP array. The variable dielectric width capacitor approach employs metal plates terminated with sharp corners to enhance local electric field and facilitate easy breakdown of the thin dielectric between the metal plates. The vertical MOSCAP array consists of a capacitor array connected in series. Both approaches were designed, simulated, fabricated, and experimentally characterized on GlobalFoundries 22 nm fully depleted silicon-oninsulator (FDSOI) technology. The designed vertical MOSCAP arrays were able to detect ESD events ≥ 6 V while the variable dielectric width capacitor based sensor is able to detect ESD voltii ages ≥ 40 V . A Bayesian method was formulated for the estimation of ESD voltage using the sensors and experimentally validated. Mathematical formulation for sensitivity and confidence in ESD voltage estimation was developed which matches the results of Monte-Carlo simulations. A sensitivity of 1 parts per million is achievable with 4 sensors for an ESD voltage detection of 7.4 V .The simulation study further indicates that the error in voltage estimation can be reduced from 25% to 8% by increasing the number of sensors from 1 to 8.Finally, a novel high-power delivery network for the Silicon interconnect fabric (Si-IF), a heterogeneous wafer-scale integration platform, is also proposed. The system is capable of 42 kW output power delivery to dielets when supplied with a 50-kW input power. Power delivery network (PDN) modelling and simulations have been carried out to determine impedance spectrum and I 2 R losses. A 100 W experimental prototype was designed and evaluated to check the feasibility of the proposed architecture.iii The dissertation of Kannan Kalappurakal Thankappan is approved.

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Section: Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

An On-Chip ESD Sensor for Use in Advanced Packaging

Kannan

Vaisband

Sahoo

et al. 2022

IEEE Trans. Compon., Packag. Manufact. Technol.

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“…Fukushima et al have introduced a fan-out wafer-level process, called Flextrate TM , for flexible biocompatible substrates [7]. The molding compound in this case is a medically graded silicone (PDMS) material.…”

Section: Bendability In Flexible Fan-out Processmentioning

confidence: 99%

“…Furthermore, they can possibly delaminated from the PDMS. Fukushima et al, have introduced special stress buffer layers to minimize stresses in metal structures [7]. Corrugated structures for Cu wires have been introduced by Hanna et al to improve the reliability of metal wires during bending [8].…”

Section: Bendability In Flexible Fan-out Processmentioning

confidence: 99%

Reliability challenges in advance packaging

Iyer

Bajwa

2018

2018 IEEE International Reliability Physics Symposium (IRPS)

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This paper highlights the packaging related reliability issues in various advanced packaging schemes such as 3-D stacking, interposers, fan-out packaging, and the more recently developed silicon interconnect fabric integration. The need for heterogeneous integration, superior electrical and thermal performance, reduction of form factor and overall systemfootprint, and integration of high-density interconnects are the main driving forces behind the development of these advanced packaging techniques. As the packaging and system integration is becoming more complex, the emphasis is mainly on improving the reliability of system-level packaging rather than the individually packaged devices.

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“…In fan-out interconnection technologies, interconnections are directly formed from the chip pads to package traces without the need for solder or similar interconnections and assembly. In one such technology, chips are placed first, followed by the formation of the redistribution layers over the reconstituted chips as a molded wafer or a large panel [8]. In this approach towards chip-embedding with wafer-level fan-out packaging, chips are assembled on a temporary carrier while facing down (1st Handler) with a release tape, followed by encapsulation.…”

Section: Introductionmentioning

confidence: 99%

Embedded-Component Planar Fan-Out Packaging for Biophotonic Applications

Hassan

Soroushiani

Abdal

et al. 2022

IEEE Open J. Nanotechnol.

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Embedded-chip planar silver-elastomer interconnect technology is developed with flexible substrates and demonstrated for on-skin biophotonic sensor applications. This approach has several benefits and is also consistent with chip-thinning where the chip thickness is 100 microns and less. The key benefits from this approach arise because both the bottom and top sides are now available as flat surfaces for 3D integration of other components. It also results in the lowest electrical parasitics compared to flipchip with adhesives or printed-ramp interconnections with surface-assembled devices. Embedding of chips in flexible carriers was accomplished with direct screen-printed interconnects onto the chip pads in substrate cavities. Silver nanoflake-loaded polyurethane is utilized in the embedded-chip packages to provide the desired lower interconnect resistance and also reliability in flexible packages under deformed configurations. Viscoelastic models were utilized to model the interconnection stresses. Planar interconnects in flexible substrates are developed with conductive silver-loaded elastomer interconnects. This approach is compared to direct chip-on-flex assembly technology for reliability under bending and high-temperature storage. The embedded-chip technology is demonstrated through biophotonic sensor applications where light sources (LEDs) and photodetectors are embedded inside the package. Functional validation in bent configuration at low curvatures is shown by measuring pulse rate and muscle activity with human subjects. By extending this technology to nanowires in elastomers, further enhancement in electrical and reliability performance can be achieved.

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“FlexTrate ^TM” — Scaled Heterogeneous Integration on Flexible Biocompatible Substrates Using FOWLP

Cited by 17 publications

References 4 publications

An On-Chip ESD Sensor for Use in Advanced Packaging

An On-Chip ESD Sensor for Use in Advanced Packaging

Reliability challenges in advance packaging

Embedded-Component Planar Fan-Out Packaging for Biophotonic Applications

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