Fixed and Adaptive Sequential Prefetching in Shared Memory Multiprocessors

Dahlgren, Fredrik; Dubois, Michel; Stenström, Per

doi:10.1109/icpp.1993.92

Cited by 108 publications

(81 citation statements)

References 11 publications

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“…Hardware and software prefetching techniques have been studied extensively [10,33,11,25,24,31,4]. Hardware-controlled prefetchers are highly effective for applications with regular data access patterns [4]; they have been integrated into all modern high-performance processors, including Intel Core i3/i5/i7, AMD Opteron and IBM POWER, and many embedded and mobile processors, such as ARM's Cortex-A9 and Cortex-A15.…”

Section: Related Workmentioning

confidence: 99%

Adaptive Runtime-Assisted Block Prefetching on Chip-Multiprocessors

García

Rico

Villavieja

et al. 2016

Int J Parallel Prog

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Memory stalls are a significant source of performance degradation in modern processors. Data prefetching is a widely adopted and well studied technique used to alleviate this problem. Prefetching can be performed by the hardware, or be initiated and controlled by software. Among software controlled prefetching we find a wide variety of schemes, including runtimedirected prefetching and more specifically runtime-directed block prefetching.This paper proposes a hybrid prefetching mechanism that integrates a software driven block prefetcher with existing hardware prefetching techniques. Our runtime-assisted software prefetcher brings large blocks of data on-chip with the support of a low cost hardware engine, and synergizes with existing hardware prefetchers that manage locality at a finer granularity. The runtime system that drives the prefetch engine dynamically selects which cache to prefetch to.Our evaluation on a set of scientific benchmarks obtains a maximum speed up of 32% and 10% on average compared to a baseline with hardware prefetching only. As a result, we also achieve a reduction of up to 18% and 3% on average in energy-to-solution.

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Section: Related Workmentioning

confidence: 99%

Adaptive Runtime-Assisted Block Prefetching on Chip-Multiprocessors

García

Rico

Villavieja

et al. 2016

Int J Parallel Prog

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“…Direction Strategy. Strategy S2 (direction) is analogous to the sequential prefetching scheme [3,18]. This direction strategy assumes that the most likely direction of the next operation can be determined.…”

Section: Prefetching Strategiesmentioning

confidence: 99%

“…Mean and exponential weight average strategies have been inspired by [2]. Direction strategy is similar to sequential prefetching strategies [3,18].…”

Section: Related Workmentioning

confidence: 99%

Prefetching for visual data exploration

Doshi

Rundensteiner

Ward

2003

Eighth International Conference on Database Systems for Advanced Applications, 2003. (DASFAA 2003). Proceedings.

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“…Software prefetching relies on the compiler to perform static program analysis and to selectively insert prefetch instructions into the executable code [16][17][18][19]. Hardware-based prefetching, on the other hand, requires no compiler support, but it does require some additional hardware connected to the cache [8][9][10][11][12][13][14][15]. This type of prefetching is designed to be transparent to the processor.…”

Section: Related Workmentioning

confidence: 99%

“…Several methods have been proposed to exploit more instruction-level parallelism in superscalar processors and to hide the latency of the main memory accesses, including speculative execution [1][2][3][4][5][6][7] and data prefetching [8][9][10][11][12][13][14][15][16][17][18][19][20][21]. To achieve high issue rates, instructions must be fetched beyond the basic block-ending conditional branches.…”

Section: Introductionmentioning

confidence: 99%

Exploiting the Prefetching Effect Provided by Executing Mispredicted Load Instructions

Sendag

Lilja

Kunkel³

2002

Euro-Par 2002 Parallel Processing

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Abstract.As the degree of instruction-level parallelism in superscalar architectures increases, the gap between processor and memory performance continues to grow requiring more aggressive techniques to increase the performance of the memory system. We propose a new technique, which is based on the wrong-path execution of loads far beyond instruction fetch-limiting conditional branches, to exploit more instruction-level parallelism by reducing the impact of memory delays. We examine the effects of the execution of loads down the wrong branch path on the performance of an aggressive issue processor. We find that, by continuing to execute the loads issued in the mispredicted path, even after the branch is resolved, we can actually reduce the cache misses observed on the correctly executed path. This wrong-path execution of loads can result in a speedup of up to 5% due to an indirect prefetching effect that brings data or instruction blocks into the cache for instructions subsequently issued on the correctly predicted path. However, it also can increase the amount of memory traffic and can pollute the cache. We propose the Wrong Path Cache (WPC) to eliminate the cache pollution caused by the execution of loads down mispredicted branch paths. For the configurations tested, fetching the results of wrong path loads into a fully associative 8-entry WPC can result in a 12% to 39% reduction in L1 data cache misses and in a speedup of up to 37%, with an average speedup of 9%, over the baseline processor.

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Fixed and Adaptive Sequential Prefetching in Shared Memory Multiprocessors

Cited by 108 publications

References 11 publications

Adaptive Runtime-Assisted Block Prefetching on Chip-Multiprocessors

Adaptive Runtime-Assisted Block Prefetching on Chip-Multiprocessors

Prefetching for visual data exploration

Exploiting the Prefetching Effect Provided by Executing Mispredicted Load Instructions

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