Exploiting the Prefetching Effect Provided by Executing Mispredicted Load Instructions

Abstract

Abstract.As the degree of instruction-level parallelism in superscalar architectures increases, the gap between processor and memory performance continues to grow requiring more aggressive techniques to increase the performance of the memory system. We propose a new technique, which is based on the wrong-path execution of loads far beyond instruction fetch-limiting conditional branches, to exploit more instruction-level parallelism by reducing the impact of memory delays. We examine the effects of the execution of loads down the wrong branch path on the performance of an aggressive issue processor. We find that, by continuing to execute the loads issued in the mispredicted path, even after the branch is resolved, we can actually reduce the cache misses observed on the correctly executed path. This wrong-path execution of loads can result in a speedup of up to 5% due to an indirect prefetching effect that brings data or instruction blocks into the cache for instructions subsequently issued on the correctly predicted path. However, it also can increase the amount of memory traffic and can pollute the cache. We propose the Wrong Path Cache (WPC) to eliminate the cache pollution caused by the execution of loads down mispredicted branch paths. For the configurations tested, fetching the results of wrong path loads into a fully associative 8-entry WPC can result in a 12% to 39% reduction in L1 data cache misses and in a speedup of up to 37%, with an average speedup of 9%, over the baseline processor.

The impact of wrong-path memory references in cache-coherent multiprocessor systems

“…As a result of these replacements, WP loads pollute the data cache [21,30], which may cause additional cache misses. Fig.…”

“…From a performance point-of-view, WP memory references can have both a positive and negative effect on the processor's performance by either prefetching data into the caches or by polluting them [21,22,30,29], respectively. To determine the potential performance impact that WP memory references have in SMP systems, we categorize the misses caused by WP loads into four groups: unused, used, direct miss, and indirect miss.…”

“…Sendag et al [30] proposed using the fully-associative wrong-path cache (WPC) to eliminate the cache pollution caused by WP references. The WPC stores data brought into the processor by WP load instructions and evicted from the L1 cache.…”

“…Previous work [1,2,6,9,13,[20][21][22][23][24][25]4,[28][29][30] studied the effects that speculatively executed memory references have on the performance of out-of-order superscalar processors. These papers yield several conclusions.…”

“…First, WP memory references may function as prefetches by bringing data into the cache that are needed later by instructions on the correct execution path [22,30,29,4]. Unfortunately, these WP memory references also increase the amount of memory traffic (i.e., increased bandwidth consumption) and can pollute the cache with cache blocks that are not referenced by instructions on the CP [21,22,30,28]. Of these two effects, cache pollution-particularly in the L2 cache-is the dominant negative effect [21,22].…”