First vertically stacked GeSn nanowire pGAAFETs with I&lt;inf&gt;on&lt;/inf&gt; = 1850μA/μm (V&lt;inf&gt;ov&lt;/inf&gt; = V&lt;inf&gt;ds&lt;/inf&gt; = −1V) on Si by GeSn/Ge CVD epitaxial growth and optimum selective etching

Huang, Yuexiang; Lu, Fung Jou; Tsou, Ya-Jui; Tsai, Chung-En; Lin, Chia-Min; Wang, Yi-Chia; Liu, C. W.

doi:10.1109/iedm.2017.8268512

Cited by 15 publications

(14 citation statements)

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“… 44 , 49 In general, literature data related to electronic properties of Ge 1– x Sn x materials with higher tin contents (>5 at%) are scarce and the provided mobility, charge carrier density or sheet resistance cannot be used to calculate the respective resistivity values, because either the required data are missing, thin films are strained or the material is p- or n-doped. 51 , 52 This paper describes for the first time the electronic properties of bottom-up grown Ge 1– x Sn x NWs integrated in two-point and four-point configuration, revealing very high conductivity values while still retaining semiconducting properties. The Ge 0.81 Sn 0.19 NWs electronic properties have been investigated in the temperature range of 10–298 K. In addition, the behavior of the devices when exposed to elevated temperatures is investigated emulating potential heating effects during device operation.…”

Section: Introductionmentioning

confidence: 97%

Electrical characterization and examination of temperature-induced degradation of metastable Ge_0.81Sn_0.19nanowires

et al. 2018

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Section: Introductionmentioning

confidence: 97%

Electrical characterization and examination of temperature-induced degradation of metastable Ge_0.81Sn_0.19nanowires

et al. 2018

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“…These results are described in [2]. If a highly scaled transistor cannot meet the requirements mentioned above, we may say that the poor short-channel performance is expected and acts as a bottleneck for further scaling [5], [6].…”

Section: Introductionmentioning

confidence: 99%

“…The reason for this requirement is to maintain gate control over the channel potential barrier height [2]- [4]. As a result, the value of the I on /I off should be 10 6 . Hence a V DIBLSS /(I on /I off ) of about 10 −4 mV is obtained.…”

Section: Introductionmentioning

confidence: 99%

Monitoring of FinFET Characteristics Using $\Delta V_{\text{DIBLSS}}/(I_{\text{on}}/I_{\text{off}})$ and $\Delta V_{\text{DIBL}}/(I_{\text{on}}/I_{\text{off}})$

Eng

Chang

et al. 2019

IEEE J. Electron Devices Soc.

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In this paper, we present a descriptive analysis of a performance index, V DIBLSS /(I on /I off), used for performance monitoring. Scaled n-and p-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) (planar and FinFET devices) are included for comparison of performance trends. Also, the simplified V DIBL /(I on /I off) for monitoring the electrical characteristics of MOSFET devices is proposed due to the "quick measurements" required in the last step of the semiconductor manufacturing process. V DIBL /(I on /I off) only accounts for drain-induced barrier lowering in its numerator and on/off current ratio in its denominator. The calculation process for V DIBL /(I on /I off) is much quicker than for V DIBLSS /(I on /I off), where we need to make an extra measurement of the value of the subthreshold swing. Performance metrics, such as I on /I off and intrinsic gain, g m × r o , are reported using V DIBLSS /(I on /I off) and V DIBL /(I on /I off). V DIBLSS of about 100 mV in scaled MOSFETs is required to ensure that the gate control is strong. Since I on /I off is a sensitive function of threshold voltage, the estimates of the V DIBLSS /(I on /I off) and V DIBL /(I on /I off) are therefore dependent on the design of threshold voltage. In planar MOSFETs, small values of V DIBLSS /(I on /I off) and V DIBL /(I on /I off) are hard to achieve. However, in FinFETs, it is easy to achieve the performance requirements due to its tri-gate structure. INDEX TERMS V DIBL /(I on /I off), V DIBLSS /(I on /I off), FinFETs, intrinsic gain, performance metrics, scaled MOSFETs.

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“…GAA structures offer excellent electrostatic and short-channel control, and the stacking of nanowires/nanosheets increases the total drive current per footprint. Si, SiGe, GeSn, and InGaAs stackedchannel FETs have been reported in the literature [10][11][12][13][14][15][16].…”

Section: Introductionmentioning

confidence: 99%

Ge/Si Multilayer Epitaxy and Removal of Dislocations from Ge-nanosheet-channel MOSFETs

Chu¹,

Chang²,

Chen³

et al. 2021

Preprint

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Horizontally stacked pure-Ge-nanosheet gate-all-around field-effect transistors (GAA FETs) were developed in this study. Large lattice mismatch Ge/Si multilayers were intentionally grown as the starting material rather than Ge/GeSi multilayers to acquire the benefits of the considerable difference in material properties of Ge and Si for realising selective etching. Flat Ge/Si multilayers were grown at a low temperature to preclude island growth. The shape of Ge nanosheets was almost retained after etching owing to the excellent selectivity. Additionally, dislocations were observed in suspended Ge nanosheets because of the absence of a Ge/Si interface and the disappearance of the dislocation-line tension force owing to the elongation of misfit dislocation at the interface. Forming gas annealing of the suspended Ge nanosheets resulted in a significant increase in the glide force compared to the dislocation-line tension force; the dislocations were easily removed because of this condition and the small size of the nanosheets. Based on this structure, a new mechanism of dislocation removal from suspended Ge nanosheet structures by annealing was described, which resulted in the structures exhibiting excellent gate control and electrical properties.

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First vertically stacked GeSn nanowire pGAAFETs with I<inf>on</inf> = 1850μA/μm (V<inf>ov</inf> = V<inf>ds</inf> = −1V) on Si by GeSn/Ge CVD epitaxial growth and optimum selective etching

Cited by 15 publications

References 5 publications

Electrical characterization and examination of temperature-induced degradation of metastable Ge_0.81Sn_0.19nanowires

Electrical characterization and examination of temperature-induced degradation of metastable Ge_0.81Sn_0.19nanowires

Monitoring of FinFET Characteristics Using $\Delta V_{\text{DIBLSS}}/(I_{\text{on}}/I_{\text{off}})$ and $\Delta V_{\text{DIBL}}/(I_{\text{on}}/I_{\text{off}})$

Ge/Si Multilayer Epitaxy and Removal of Dislocations from Ge-nanosheet-channel MOSFETs

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First vertically stacked GeSn nanowire pGAAFETs with I<inf>on</inf> = 1850μA/μm (V<inf>ov</inf> = V<inf>ds</inf> = −1V) on Si by GeSn/Ge CVD epitaxial growth and optimum selective etching

Cited by 15 publications

References 5 publications

Electrical characterization and examination of temperature-induced degradation of metastable Ge0.81Sn0.19nanowires

Electrical characterization and examination of temperature-induced degradation of metastable Ge0.81Sn0.19nanowires

Monitoring of FinFET Characteristics Using $\Delta V_{\text{DIBLSS}}/(I_{\text{on}}/I_{\text{off}})$ and $\Delta V_{\text{DIBL}}/(I_{\text{on}}/I_{\text{off}})$

Ge/Si Multilayer Epitaxy and Removal of Dislocations from Ge-nanosheet-channel MOSFETs

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Electrical characterization and examination of temperature-induced degradation of metastable Ge_0.81Sn_0.19nanowires

Electrical characterization and examination of temperature-induced degradation of metastable Ge_0.81Sn_0.19nanowires