First Vertical Hall Device in standard 0.35 μm CMOS technology

Capteur ECG intelligent pour la synchronisation des séquences en IRM et le monitorage des patients

“…Les capteurs verticaux déve-loppés en technologie standard CMOS à cette occasion sont une réelle innovation technologique (Fig. 1b) [12][13][14][15].…”

Intrinsic limits of the sensitivity of CMOS integrated vertical Hall devices

“…The VHD in Fig. 4 is a five-contacts vertical Hall device [11,14]. We place only two point-like sensing contacts and three small enough biasing contacts (700 nm wide and 150 nm deep) in order to be free from short-circuit effect.…”

“…These markers will also appear in the simulation results for a better understanding of the plots. We can notice that in planar technology, it is possible to place the two sensing contacts in Z A and Z C or in Z D and Z E , respectively as explained in [14]. One will choose the first configuration or the second one depending on the depth of the N-well that is provided by the technology [14].…”

“…We can notice that in planar technology, it is possible to place the two sensing contacts in Z A and Z C or in Z D and Z E , respectively as explained in [14]. One will choose the first configuration or the second one depending on the depth of the N-well that is provided by the technology [14]. The dimensions of the simulated device correspond to those usually used for VHD integrated in high voltage CMOS technologies.…”

“…Nevertheless, it has been shown that the spinning-current technique is less effective for a VHD than for a HHD due to the more complex current flow geometry that settles in the VHD [13]. The state of the art performances for CMOS integrated VHD are residual offset of about 400 T and resolution around 100 T over 1.6 kHz bandwidth [13,14]. On the way to an optimized CMOS integrated VHD, the uneven influence of junction field effect on the offset and on the sensitivity of the VHD has been recently studied in order to propose suitable biasing of the vertical structures [15].…”