First Integration of 10-V CMOS Logic Circuit, 20-V Gate Driver, and 600-V VDMOSFET on a 4H-SiC Single Chip

Tsui, Bing-Yue; Hung, Che Lun; Tsai, Tsung-Che; Tsui, Yu-Chia; Wang, T. W.; Wen, Y. X.; Shih, Chung-Ting; Wang, Jen-Chun; Lin, Li-Jung; Chu, Ko-Tsung; Chen, Po-Hsiang

doi:10.1109/ispsd49238.2022.9813677

Cited by 11 publications

(2 citation statements)

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“…Several SiC CMOS circuits have been reported in literatures [2][3][4][5][6]. Recently, integration of both vertical power MOSFET and CMOS gate buffer on a single SiC chip has been reported [7,8]. Though with normal switching operation controlled by low-voltage SiC CMOS devices, the reliability of the CMOS devices has not been disclosed.…”

Section: Introductionmentioning

confidence: 99%

Bias-Induced Instability of 4H-SiC CMOS

Wen

Tsui

2023

MSF

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4H-SiC complementary metal-oxide-semiconductor (CMOS) devices for control circuit applications have been reported extensively, however, the electrical stability, even with interface optimization processes, degrades significantly after bias stress. In this paper, we performed both positive and negative bias stress on planar SiC NMOSFETs and PMOSFETs fabricated with pure (non-diluted) and N2-diluted NO post-oxidation annealing (POA) processes. The test results indicate the existence of positive hole traps might be the culprit that leads to electrical characteristics instability during operation and pure NO annealing is effective to reduce the instability.

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Section: Introductionmentioning

confidence: 99%

Bias-Induced Instability of 4H-SiC CMOS

Wen

Tsui

2023

MSF

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“…10, 10-V CMOS logic circuits, 20-V CMOS gate drivers, and 600-V vertical double-diffused MOSFETs were integrated in a single chip for the first time to realize smart power 4H-SiC ICs. 10 Multiple threshold voltage (V th ) or gate oxide options increase circuit design flexibility. Circuits with lower leakage current can be realized using MOSFETs with higher V th ; however, the circuit's speed would be reduced.…”

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confidence: 99%

Design, Process, and Characterization of Complementary Metal–Oxide–Semiconductor Circuits and Six-Transistor Static Random-Access Memory in 4H-SiC

Hung¹,

Tsui²,

Tsai³

et al. 2022

ECS J. Solid State Sci. Technol.

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In this study, the performance of complementary metal–oxide–semiconductor (MOS) circuits fabricated on SiC substrates was investigated by designing several digital and analog circuits, and a unique process flow was developed to integrate n-type MOS (NMOS) and p-type MOS (PMOS) transistors with low and high threshold voltages (Vth) into a single chip. A detailed process flow with local oxidation of SiC isolation and a dual gate oxide with a compromised gate dielectric are presented. The performance of NMOS field-effect transistors (FETs) and PMOSFETs with low and high Vth were characterized in detail. Lateral MOS capacitors were also fabricated in the same chip to explore the characteristics of the gate dielectric. Several common logic gate components were fabricated and tested at elevated temperatures to demonstrate the normal function of these elements in a digital circuit. Static random-access memory (SRAM) cells were designed and optimized through simulation. Characterizations of all the circuit blocks are presented to demonstrate the capability of these circuits in harsh environments.

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