First Demonstration of Low Temperature (≤500°C) CMOS Devices Featuring Functional RO and SRAM Bitcells toward 3D VLSI Integration

Fenouillet-Béranger, C.; Brunet, Laurent; Batude, P.; Brévard, L.; Garros, X.; Frutuoso, T. Mota; Cassé, M.; Lugo, J.; Lacord, J.; Bosch, D.; Bernard, N.; Magalhaes-Lucas, A.; Ribotta, M.; Sklénard, B.; Milési, F.; Kies, R.; Romano, G.; Acosta-Alba, P.; Kerdilès, S.; Tavernier, Aurélien; Vizioz, C.; Besson, P.; Gassilloud, R.; Kanyandekwe, J.; Cooper, David; Lapras, V.; Kim, W-H.; Sasaki, Y.; Oh, Sangsuk; Kang, Purum; Sw, Lee; Na, H.; Arcamone, Julien; Andrieu, F.

doi:10.1109/vlsitechnology18217.2020.9265092

Cited by 9 publications

(4 citation statements)

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“…T hree-dimensional (3D) integration of transistors [1][2][3][4][5][6][7][8] enables further increment of chip density and performance improvement while alleviating scaling difficulties. Applicable thermal budget is then severely restricted because the bottom-layer transistors must be preserved during the thermal processing of the upper-layer ones.…”

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confidence: 99%

Microsecond non-melt UV laser annealing for future 3D-stacked CMOS

Tabata

Rozé

Thuries

et al. 2022

Appl. Phys. Express

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Three-dimensional (3D) CMOS technology encourages the use of UV laser annealing (UV-LA) because the shallow absorption of UV light into materials and the process timescale typically from nanoseconds (ns) to microseconds (µs) strongly limit the vertical heat diffusion. In this work, µs UV-LA solid phase epitaxial regrowth (SPER) demonstrated an active carrier concentration surpassing 1 × 1021 at./cm3 in an arsenic ion-implanted silicon-on-insulator substrate. After the subsequent ns UV-LA known for improving CMOS interconnect, only a slight (⁓5%) sheet resistance increase was observed. The results open a possibility to integrate UV-LA at different stages of 3D-stacked CMOS.

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confidence: 99%

Microsecond non-melt UV laser annealing for future 3D-stacked CMOS

Tabata

Rozé

Thuries

et al. 2022

Appl. Phys. Express

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“…Nowadays 3D-integrated electronic devices are emerging to further explore alternative scaling paths of transistors (1)(2)(3)(4)(5)(6)(7) or to add another functionality on the same chip especially in the back-end-of-line stage (8)(9). However, vertical stacking of multiple functional layers brings a very challenging limitation of the thermal budget applicable to the top-tier devices (e.g., 500 °C for 2 h in Refs.…”

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confidence: 99%

Wrinkles Emerging in SiO₂/Si Stack during UV Nanosecond Laser Anneal

et al. 2021

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UV nanosecond pulsed laser annealing (UV-NLA) is demonstrating clear benefits in the emerging 3D-integrated electronic devices, where the allowed thermal budget is strictly limited to preserve underlying device performance. A possible drawback of UVNLA is that melting a solid substrate covered by a dielectric layer, which can be found in typical electronic device structures, induces wrinkles on the surface and may be an issue for subsequent processes. In this study, UV-NLA is performed in SiO2/Si structures to systematically investigate the emergence of wrinkles. A classical analytical model shows a good agreement with our experimental results if a fitting coefficient is involved. Interestingly, its value is rapidly increasing for a thinner SiO2 film, while it becomes closer to unity for a thicker SiO2 film. This might infer a possible discrepancy of the material properties taken from literature and those of real industrial thin SiO2 films.

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“…Nowadays 3D-integrated electronic devices are emerging to further explore alternative scaling paths of transistors [1][2][3][4][5][6][7] or to add another functionality on the same chip especially in the back-end-ofline stage. 8,9 However, vertical stacking of multiple functional layers brings a very challenging limitation of the thermal budget applicable to the top-tier devices (e.g., 500 °C for 2 h in Refs.…”

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confidence: 99%

Non-Equilibrium Growth of Surface Wrinkles Emerging in an SiO₂/Si Stack during Si Melting Induced by UV Nanosecond Pulsed Laser Annealing

Karmous

Rozé

Raynal³

et al. 2022

ECS J. Solid State Sci. Technol.

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UV nanosecond pulsed laser annealing (UV-NLA) is demonstrating clear benefits in emerging 3D-integrated electronic devices, where the allowed thermal budget is strictly limited to preserve underlying device performance. A possible drawback of UV-NLA is that melting a solid substrate covered by a dielectric layer, which can be found in typical electronic device structures, induces wrinkles on the surface and may be an issue for subsequent processes. In this study, UV-NLA is performed in SiO2/Si structures to systematically investigate the emergence of wrinkles. A classical analytical model shows good agreement with our experimental results if a fitting coefficient is involved. Interestingly, its value rapidly increases for a thinner SiO2 film, whereas it becomes closer to unity for a thicker SiO2 film. This might infer a possible discrepancy of the material properties taken from literature and those of real industrial thin SiO2 films. The degree of the initial SiO2 film stress being negligible compared to the SiO2 shear modulus, its impact on the growth of wrinkles is not significant in our experiment.

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First Demonstration of Low Temperature (≤500°C) CMOS Devices Featuring Functional RO and SRAM Bitcells toward 3D VLSI Integration

Cited by 9 publications

References 0 publications

Microsecond non-melt UV laser annealing for future 3D-stacked CMOS

Microsecond non-melt UV laser annealing for future 3D-stacked CMOS

Wrinkles Emerging in SiO₂/Si Stack during UV Nanosecond Laser Anneal

Non-Equilibrium Growth of Surface Wrinkles Emerging in an SiO₂/Si Stack during Si Melting Induced by UV Nanosecond Pulsed Laser Annealing

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First Demonstration of Low Temperature (≤500°C) CMOS Devices Featuring Functional RO and SRAM Bitcells toward 3D VLSI Integration

Cited by 9 publications

References 0 publications

Microsecond non-melt UV laser annealing for future 3D-stacked CMOS

Microsecond non-melt UV laser annealing for future 3D-stacked CMOS

Wrinkles Emerging in SiO2/Si Stack during UV Nanosecond Laser Anneal

Non-Equilibrium Growth of Surface Wrinkles Emerging in an SiO2/Si Stack during Si Melting Induced by UV Nanosecond Pulsed Laser Annealing

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Product

Resources

About

Wrinkles Emerging in SiO₂/Si Stack during UV Nanosecond Laser Anneal

Non-Equilibrium Growth of Surface Wrinkles Emerging in an SiO₂/Si Stack during Si Melting Induced by UV Nanosecond Pulsed Laser Annealing