First Demonstration of GAA Monolayer-MoS<sub>2</sub> Nanosheet nFET with 410μA μ m ID 1V VD at 40nm gate length

Chung, Ying Chien; Chou, Bo-Jhih; Hsu, Chia-Kuei; Yun, Wei-Sheng; Li, Mingyang; Su, Sheng-Kai; Liao, Yu-Tsung; Lee, Meng-Chien; Huang, Guo–Wei; Liew, San-Lin; Shen, Yun-Yang; Chang, Wen‐Hao; Chen, Chien‐Wei; Kei, Chi-Chung; Wang, Han; Wong, H.-S. Philip; Lee, T. Y.; Chien, Chao–Hsin; Cheng, Chuan; Radu, Iuliana

doi:10.1109/iedm45625.2022.10019563

Cited by 30 publications

(14 citation statements)

References 3 publications

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“…Hitesh et al demonstrated a 3-level MBCFET, which consisted of three vertically stacked 1L-MoS 2 channels and achieved a saturation current of 174.9 μA. 227 In 2022, TSMC proposed a practical integration flow for stacked 2D nanosheets and demonstrated a nanosheet GAA monolayer-MoS 2 FET with an on-state current of 410 μA μm −1 at V DS = 1 V. 228 Wu's group showed that monolithic 3D stacking comple-mentary FETs (CFETs) based on CVD-grown 2D material channels can be used for 4T SRAM and 16T half-adder. 229 Large-Scale Demonstrations.…”

Section: Performace Optimization and Integration Of 2d Transistorsmentioning

confidence: 99%

Two-Dimensional Semiconductors and Transistors for Future Integrated Circuits

Yin,

Cheng,

Ding

et al. 2024

ACS Nano

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Silicon transistors are approaching their physical limit, calling for the emergence of a technological revolution. As the acknowledged ultimate version of transistor channels, 2D semiconductors are of interest for the development of post-Moore electronics due to their useful properties and all-in-one potentials. Here, the promise and current status of 2D semiconductors and transistors are reviewed, from materials and devices to integrated applications. First, we outline the evolution and challenges of silicon-based integrated circuits, followed by a detailed discussion on the properties and preparation strategies of 2D semiconductors and van der Waals heterostructures. Subsequently, the significant progress of 2D transistors, including device optimization, large-scale integration, and unconventional devices, are presented. We also examine 2D semiconductors for advanced heterogeneous and multifunctional integration beyond CMOS. Finally, the key technical challenges and potential strategies for 2D transistors and integrated circuits are also discussed. We envision that the field of 2D semiconductors and transistors could yield substantial progress in the upcoming years and hope this review will trigger the interest of scientists planning their next experiment.

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Section: Performace Optimization and Integration Of 2d Transistorsmentioning

confidence: 99%

Two-Dimensional Semiconductors and Transistors for Future Integrated Circuits

Yin,

Cheng,

Ding

et al. 2024

ACS Nano

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“…A highly tunable doping level with negligible material structural damage is an ideal condition for achieving controllable and effective doping [463]. Although 2D transistor devices have made great progress in the past few years [428,429,464], they are mainly aimed at n-type devices, and achieving high-performance p-type devices remains a major challenge in building low-power CMOS architectures [437,459,465]. Ideally, by using appropriate and reliable doping techniques, intrinsic 2D channel materials can be transformed into both p-type and n-type transistors, as shown in Figure 40(a), which has been initially achieved in materials systems such as WSe2 and MoTe2 [466][467][468], and demonstrated reconfigurable electronic devices and circuits [468,469].…”

Section: Doping Strategymentioning

confidence: 99%

Two-dimensional materials for future information technology: status and prospects

Qiu,

Yu,

Zhao

et al. 2024

Sci. China Inf. Sci.

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Over the past 70 years, the semiconductor industry has undergone transformative changes, largely driven by the miniaturization of devices and the integration of innovative structures and materials. Two-dimensional (2D) materials like transition metal dichalcogenides (TMDs) and graphene are pivotal in overcoming the limitations of silicon-based technologies, offering innovative approaches in transistor design and functionality, enabling atomic-thin channel transistors and monolithic 3D integration. We review the important progress in the application of 2D materials in future information technology, focusing in particular on microelectronics and optoelectronics. We comprehensively summarize the key advancements across material production, characterization metrology, electronic devices, optoelectronic devices, and heterogeneous integration on silicon. A strategic roadmap and key challenges for the transition of 2D materials from basic research to industrial development are outlined. To facilitate such a transition, key technologies and tools dedicated to 2D materials must be developed to meet industrial standards, and the employment of AI in material growth, characterizations, and circuit design will be essential. It is time for academia to actively engage with industry to drive the next 10 years of 2D material research.

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“…With the VRRAM variations taken into consideration, we show that for the set process, the MoS 2 FET can drive up to 8 layers of VRRAMs; and for the reset process, it can drive up to 9 layers of VRRAMs in parallel in the 1T-nR configuration. The parallel driving capability can be further improved by decreasing the contact resistance, using 2D semiconductors with a higher carrier mobility, or constructing gate-all-around transistors by stacking 2D nanosheets 60 .…”

Section: Cross-layer Modeling Of the Monolithic 3d Structurementioning

confidence: 99%

Monolithic 3D integration of 2D transistors and vertical RRAMs in 1T–4R structure for high-density memory

Xie,

Jia,

Nie

et al. 2023

Nat Commun

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Emerging data-intensive computation has driven the advanced packaging and vertical stacking of integrated circuits, for minimized latency and energy consumption. Yet a monolithic three-dimensional (3D) integrated structure with interleaved logic and high-density memory layers has been difficult to achieve due to challenges in managing the thermal budget. Here we experimentally demonstrate a monolithic 3D integration of atomically-thin molybdenum disulfide (MoS2) transistors and 3D vertical resistive random-access memories (VRRAMs), with the MoS2 transistors stacked between the bottom-plane and top-plane VRRAMs. The whole fabrication process is integration-friendly (below 300 °C), and the measurement results confirm that the top-plane fabrication does not affect the bottom-plane devices. The MoS2 transistor can drive each layer of VRRAM into four resistance states. Circuit-level modeling of the monolithic 3D structure demonstrates smaller area, faster data transfer, and lower energy consumption than a planar memory. Such platform holds a high potential for energy-efficient 3D on-chip memory systems.

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First Demonstration of GAA Monolayer-MoS₂ Nanosheet nFET with 410μA μ m ID 1V VD at 40nm gate length

Cited by 30 publications

References 3 publications

Two-Dimensional Semiconductors and Transistors for Future Integrated Circuits

Two-Dimensional Semiconductors and Transistors for Future Integrated Circuits

Two-dimensional materials for future information technology: status and prospects

Monolithic 3D integration of 2D transistors and vertical RRAMs in 1T–4R structure for high-density memory

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First Demonstration of GAA Monolayer-MoS2 Nanosheet nFET with 410μA μ m ID 1V VD at 40nm gate length

Cited by 30 publications

References 3 publications

Two-Dimensional Semiconductors and Transistors for Future Integrated Circuits

Two-Dimensional Semiconductors and Transistors for Future Integrated Circuits

Two-dimensional materials for future information technology: status and prospects

Monolithic 3D integration of 2D transistors and vertical RRAMs in 1T–4R structure for high-density memory

Contact Info

Product

Resources

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First Demonstration of GAA Monolayer-MoS₂ Nanosheet nFET with 410μA μ m ID 1V VD at 40nm gate length