First Demonstration of CMOS Inverter and 6T-SRAM Based on GAA CFETs Structure for 3D-IC Applications

Chang, S. W.; Li, J.-H.; Huang, Min-Wei; Huang, Yi‐Pai; Huang, Shao-Chang; Wang, H.-C.; Huang, Yan-Jia; Wang, J.-Y.; Yu, Luqi; Huang, Yu-Chieh; Hsueh, Fu-Kuo; Sung, Po-Jung; Wu, C. M.; C.-Y., W.; Kao, Kuo-Hsing; Lee, Y. J.; Lin, Cheng-Li; Chuang, Ricky W.; Huang, Kun-Ping; Samukawa, Seiji; Li, Y.; Lee, W. H.; Chu, T-Y.; Chao, Tien−Sheng; Huang, Guo–Wei; Wu, Wen−Fa; Li, J. Y.; Shieh, Jia‐Min; Yeh, Wen–Kuan; Wang, Y.-H.; Lu, Darsen D.; Wang, C.-J.; Lin, Nathan C.; Su, Chun Jung; Lo, S.-H.; Huang, Hao

doi:10.1109/iedm19573.2019.8993525

Cited by 50 publications

(22 citation statements)

References 2 publications

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“…1 (a) and (c) show the 3-D bird's eye view of the CFET and the standard CMOS with separate n/pFETs, respectively. The stacked structure of nanosheet in CFET is fabricated from SiO2/ Si/ SiO2/ Si structure as same as reference [3]. It is assumed that pFET and nFET are located in the upper and lower layers, respectively [3].…”

Section: Modeling Methodologymentioning

confidence: 99%

“…Thus, to further reduce the area of devices in layout, lots of device structures like forksheet FET, complementary field-effect transistor (CFET) have been suggested [1]- [7]. Among them, a CFET, which stacked n-type NSHFET and p-type NSHFET vertically with a shared gate for CMOS logic operation in single device, has recently been researched by Intel, IMEC and NARLab [3]- [5]. They demonstrate that CFET is one of the promising techniques beyond FinFET and NSHFET, which can effectively reduce a device area with high compatibility to conventional FinFET and NSHFET fabrication process [3]- [5].…”

Section: Introductionmentioning

confidence: 99%

“…Among them, a CFET, which stacked n-type NSHFET and p-type NSHFET vertically with a shared gate for CMOS logic operation in single device, has recently been researched by Intel, IMEC and NARLab [3]- [5]. They demonstrate that CFET is one of the promising techniques beyond FinFET and NSHFET, which can effectively reduce a device area with high compatibility to conventional FinFET and NSHFET fabrication process [3]- [5]. Thus, there have been several researches on CMOS inverter operation of CFET, but they include buried power rail (BPR) technique which is unusual in industry [2], [8].…”

Section: Introductionmentioning

confidence: 99%

“…Thus, there have been several researches on CMOS inverter operation of CFET, but they include buried power rail (BPR) technique which is unusual in industry [2], [8]. Except them, most of the researches on general CFET only focus on developing fabrication technique and do not deal with CMOS inverter operation specifically [3]- [5]. In case of NARLab, they predict that CFET can improve CMOS inverter performances when compared to standard CMOS with NSHFETs, but there is no analysis on the reason [5].…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Performance Analysis on Complementary FET (CFET) Relative to Standard CMOS With Nanosheet FET

Jung

Jang

Min

et al. 2022

IEEE J. Electron Devices Soc.

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For the first time, by using 3-D TCAD, the advantage of using complementary FET (CFET), which has vertically stacked nanosheet nFET and pFET with shared gate, is compared to standard CMOS with nanosheet FETs in perspective of CMOS inverter performance. The comparative study on CMOS operation was performed between CFET and standard CMOS in 3-nm technology node. The results indicate that, when both devices have identical DC electrical characteristics, using CFET can increase the frequency by ~2.3% in iso-power and decrease power by ~7.3% in iso-frequency compared to the standard CMOS with separate n/pFETs while effectively reducing the area by ~55%. It is also investigated that such results are due to the approximately 4.5% low effective capacitance (Ceff) of the CFET compared to the standard CMOS. This low Ceff of CFET arises from the stacked structure, which causes the gate-fringe electric field overlap and short via pitch between nFET and pFET. Furthermore, the performance of CFET by different n/pFET separation distances, channel lengths, and widths are analyzed. This study can provide critical insight into the performance improvement by using CFET for sub 3-nm technology.

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Section: Modeling Methodologymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Performance Analysis on Complementary FET (CFET) Relative to Standard CMOS With Nanosheet FET

Jung

Jang

Min

et al. 2022

IEEE J. Electron Devices Soc.

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“…The theoretical simulation results demonstrate that carbon nanotube-based monolithic three-dimensional integrated circuits have 1000 times performance and power consumption advantages over the traditional integrated circuits. Combined with the feature mentioned above that carbon nanotube can be used to construct a variety of functional devices, it is conducive to realizing the integration of sensing, memory, and computing chip in three-dimensional architecture just like the structure shown in Figure 15 [75][76][77][78][79][80][81].…”

Section: Challenge and Outlookmentioning

confidence: 99%

Carbon nanotube-based CMOS transistors and integrated circuits

Xie

Zhang

2021

Sci. China Inf. Sci.

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Over the last sixty years, the scaling of silicon-based complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) have promoted the rapid development of microelectronic technology. However, the development of Si CMOS technology is currently subject to serious challenges from various aspects such as physics limit, cost, and power consumption, and is becoming increasingly difficult. Material innovation is exerting an ever-greater role in the integrated circuit design. By looking for thinner semiconductor materials with higher mobility as the active layer to construct smaller and higher-performance transistors, it is possible to further stimulate transistors and integrated circuits on performance, density, power dissipation, and functions. In 1991, Iijima discovered carbon nanotubes (CNTs). Due to its excellent electrical properties and intrinsic nano-scale size, CNT has been considered by academia and industry to have great potential to replace silicon materials in the future for the extremely scaled technology nodes or novel electronic applications. This paper reviews the latest advancements in CNT-based electronics research. Finally, the challenges and pathways for nanotube transistors to transition into commercial applications are discussed.

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Toward monolithic growth integration of nanowire electronics in 3D architecture: a review

Liang,

Hu,

2023

Sci. China Inf. Sci.

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First Demonstration of CMOS Inverter and 6T-SRAM Based on GAA CFETs Structure for 3D-IC Applications

Cited by 50 publications

References 2 publications

Performance Analysis on Complementary FET (CFET) Relative to Standard CMOS With Nanosheet FET

Performance Analysis on Complementary FET (CFET) Relative to Standard CMOS With Nanosheet FET

Carbon nanotube-based CMOS transistors and integrated circuits

Toward monolithic growth integration of nanowire electronics in 3D architecture: a review

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