First Demonstration of 25-nm Quad Interface p-MTJ Device With Low Resistance-Area Product MgO and Ten Years Retention for High Reliable STT-MRAM

Nishioka, K.; Miura, Shigeto; Honjo, Haruo; Inoue, Hirofumi; Watanabe, Takahito; Nasuno, T.; Naganuma, Hiroshi; Nguyen, Thu-Thuy; Noguchi, Y.; Yasuhira, M.; Ikeda, Shoji; Endoh, Tetsuo

doi:10.1109/ted.2021.3074103

Cited by 12 publications

(4 citation statements)

References 22 publications

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“…Terminals T2-T4 (T4 grounded, GND) are used to apply the bias voltage Vb for VCMA. Terminals T1-T2 are used for STT, and terminals T1-T3 for SOT [28][29][30][31][32][33][34].…”

Section: Device Operation and Theoretical Detailsmentioning

confidence: 99%

Random Bitstream Generation Using Voltage-Controlled Magnetic Anisotropy and Spin Orbit Torque Magnetic Tunnel Junctions

Liu

Kwon

Bessler

et al. 2022

IEEE J. Explor. Solid-State Comput. Devices Circuits

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Probabilistic computing using random number generators (RNGs) can leverage the inherent stochasticity of nanodevices for system-level benefits. Device candidates for this application need to produce highly random "coinflips" while also having tunable biasing of the coin. The magnetic tunnel junction (MTJ) has been studied as an RNG due to its thermally-driven magnetization dynamics, often using spin transfer torque (STT) current amplitude to control the random switching of the MTJ free layer magnetization, here called the stochastic write method. There are additional knobs to control the MTJ-RNG, including voltage-controlled magnetic anisotropy (VCMA) and spin orbit torque (SOT), and there is need to more systematically study and compare these methods. We build an analytical model of the MTJ to characterize using VCMA and SOT to generate random bit streams. The results show that both methods produce high quality, uniformly distributed bitstreams. Biasing the bitstreams using either STT current or an applied magnetic field shows a sigmoidal distribution vs. bias amplitude for both VCMA and SOT, compared to less sigmoidal for stochastic write. The energy consumption per sample is calculated to be 0.1 pJ (SOT), 1 pJ (stochastic write), and 20 pJ (VCMA), revealing the potential energy benefit of using SOT and showing using VCMA may require higher damping materials. The generated bitstreams are then applied to two tasks: generating an arbitrary probability distribution and using the MTJ-RNGs as stochastic neurons to perform simulated annealing, where both VCMA and SOT methods show the ability to effectively minimize the system energy with small delay and low energy. These results show the flexibility of the MTJ as a true RNG and elucidate design parameters for optimizing the device operation for applications.

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“…Terminals T2-T4 (T4 grounded, GND) are used to apply the bias voltage Vb for VCMA. Terminals T1-T2 are used for STT, and terminals T1-T3 for SOT [28][29][30][31][32][33][34].…”

Section: Device Operation and Theoretical Detailsmentioning

confidence: 99%

Random Bitstream Generation Using Voltage-Controlled Magnetic Anisotropy and Spin Orbit Torque Magnetic Tunnel Junctions

Liu

Kwon

Bessler

et al. 2022

IEEE J. Explor. Solid-State Comput. Devices Circuits

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“…This can be implemented in RRAM by changing the cell drivers that are used for writing. For STT-MRAM, the device stack can be tailored specifically so that the difference between HRS and LRS becomes larger, thus increasing the HRS/LRS ratio [25].…”

Section: B Improvementmentioning

confidence: 99%

PVT Analysis for RRAM and STT-MRAM-based Logic Computation-in-Memory

Fieback

Münch

Gebregiorgis

et al. 2022

2022 IEEE European Test Symposium (ETS)

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Emerging non-volatile resistive memories like Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) and Resistive RAM (RRAM) are in the focus of today's research. They offer promising alternative computing architectures such as computation-in-memory (CiM) to reduce the transfer overhead between CPU and memory, usually referred to as the memory wall, which is present in all von Neumann architectures. A multitude of architectures with CiM capabilities are based on these devices, due to their inherent resistive behavior and thus their ability to perform calculation directly within the memory, and thus without invoking the CPU at all. However, emerging memories are sensitive to Process, Voltage and Temperature (PVT) variations. This sensitivity has an even larger impact on CiM architectures. In this paper, we analyze and compare the impact of PVT variations on STT-MRAM and RRAM-based CiM architectures. We perform a sensitivity analysis to identify which parts of the CiM structure are most susceptible to PVT variations, for each technology. Based on these analyses, we recommend that STT-MRAM is used in highperformance CiM, while RRAM is used for edge CiM.

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“…23,26,27) To increase the IPMA and suppress the thermal fluctuation, a double interface (Double-MTJs) was used in the 3X nm generation 28) and a quad interface (Quad-MTJs) was used in the 2X nm generation. 29) In the optimized stacking structure of the Quad-MTJs, even with a junction diameter of 18 nm, data retention of 10 years and rewriting times approaching 1 trillion were achieved simultaneously. 30) Moreover, the hexa-interface (Hexa-MTJs) demonstrated large thermal stability as well as solder reflow capability (260 °C) for targeting eFlash-type MRAM.…”

Section: Introductionmentioning

confidence: 97%

Spintronics memory using magnetic tunnel junction for X nm-generation

Naganuma

2023

Jpn. J. Appl. Phys.

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The feasibility of X nm-generation scaling with magnetic tunnel junctions (MTJs) of spintronic memory is aimed at keeping up with state-of-the-art transistor scaling. Magnetocrystalline anisotropy, shape magnetic anisotropy, and multi-interfacial magnetic anisotropy have been proposed to overcome thermal fluctuation even at the X nm generation. The high magnetocrystalline anisotropy of the L10-ordered alloy combined with graphene as a tunneling barrier in the MTJs was the main focus in this study, and their potential for scaling for both 10-year data retention and nanosecond writing efficiency by micromagnetic simulation is investigated. Data retention of 10 years and high-speed writing of 2.2 ns are achieved in the MTJs with a junction diameter of 7 nm.

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First Demonstration of 25-nm Quad Interface p-MTJ Device With Low Resistance-Area Product MgO and Ten Years Retention for High Reliable STT-MRAM

Cited by 12 publications

References 22 publications

Random Bitstream Generation Using Voltage-Controlled Magnetic Anisotropy and Spin Orbit Torque Magnetic Tunnel Junctions

Random Bitstream Generation Using Voltage-Controlled Magnetic Anisotropy and Spin Orbit Torque Magnetic Tunnel Junctions

PVT Analysis for RRAM and STT-MRAM-based Logic Computation-in-Memory

Spintronics memory using magnetic tunnel junction for X nm-generation

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