2021
DOI: 10.1109/ted.2021.3074103
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First Demonstration of 25-nm Quad Interface p-MTJ Device With Low Resistance-Area Product MgO and Ten Years Retention for High Reliable STT-MRAM

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Cited by 12 publications
(4 citation statements)
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“…Terminals T2-T4 (T4 grounded, GND) are used to apply the bias voltage Vb for VCMA. Terminals T1-T2 are used for STT, and terminals T1-T3 for SOT [28][29][30][31][32][33][34].…”
Section: Device Operation and Theoretical Detailsmentioning
confidence: 99%
“…Terminals T2-T4 (T4 grounded, GND) are used to apply the bias voltage Vb for VCMA. Terminals T1-T2 are used for STT, and terminals T1-T3 for SOT [28][29][30][31][32][33][34].…”
Section: Device Operation and Theoretical Detailsmentioning
confidence: 99%
“…This can be implemented in RRAM by changing the cell drivers that are used for writing. For STT-MRAM, the device stack can be tailored specifically so that the difference between HRS and LRS becomes larger, thus increasing the HRS/LRS ratio [25].…”
Section: B Improvementmentioning
confidence: 99%
“…23,26,27) To increase the IPMA and suppress the thermal fluctuation, a double interface (Double-MTJs) was used in the 3X nm generation 28) and a quad interface (Quad-MTJs) was used in the 2X nm generation. 29) In the optimized stacking structure of the Quad-MTJs, even with a junction diameter of 18 nm, data retention of 10 years and rewriting times approaching 1 trillion were achieved simultaneously. 30) Moreover, the hexa-interface (Hexa-MTJs) demonstrated large thermal stability as well as solder reflow capability (260 °C) for targeting eFlash-type MRAM.…”
Section: Introductionmentioning
confidence: 97%