FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud

Karandikar, Sagar; Mao, Howard; Kim, Dong-Gyu; Biancolin, David; Amid, Alon; Lee, Dayeol; Pemberton, Nathan; Amaro, Emmanuel; Colin, Stéphane; Chopra, Aditya; Huang, Qijing; Kovacs, Kyle; Nikolić, Borivoje; Bachrach, Jonathan; Asanović, Krste

doi:10.1109/mm.2019.2910175

Cited by 11 publications

(9 citation statements)

References 10 publications

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“…Commonly-used platforms for emulating digital chip designs include Cadence Palladium [4], Synopsys ZeBu [5], and Mentor Veloce [6]. There is also an open-source framework, FireSim, that can emulate warehouse-scale networks of processors at RTL level using cloud-based FPGAs [7].…”

Section: Related Workmentioning

confidence: 99%

An Open-Source Framework for FPGA Emulation of Analog/Mixed-Signal Integrated Circuit Designs

Herbst

Rutsch

Ecker

et al. 2022

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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This paper presents an open-source framework for emulating mixed-signal chip designs on an FPGA. It includes a Python-based synthesizable model generator for mixed-signal blocks (msdsl), a fixed-and floating-point synthesizable Sys-temVerilog library for representing real numbers (svreal), and a Python-based tool that generates emulator control infrastructure and automates the FPGA build process (anasymod). The framework includes features for efficiently modeling analog dynamics, nonlinearity, and noise, often making use of compile-time caching to reduce the required computational resources of the FPGA. We demonstrate the framework's generality by discussing three applications: a high-speed link receiver (DragonPHY), a firmware-controlled flyback converter, and an NFC-powered chip. Our framework makes it easy to emulate these systems, while providing runtimes 2-3 orders of magnitude faster than CPU simulations with real number functional models.

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Section: Related Workmentioning

confidence: 99%

An Open-Source Framework for FPGA Emulation of Analog/Mixed-Signal Integrated Circuit Designs

Herbst

Rutsch

Ecker

et al. 2022

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…The generator emits synthesizable Verilog which is then automatically compiled and simulated using a software RTL simulator or an FPGA-accelerated simulator for the students to characterize program execution behaviors across the different memory hierarchies tooling for FPGA prototyping, the students face the challenge of distorted timing accuracy at the periphery and system level of FPGA systems. We use the FireSim [28] FPGA-accelerated simulation platform to enable execution of long-running RTLbased simulations. FireSim is a research platform, originally designed to simulate data-center scale computing clusters at cycle-accuracy with RTL-level detail.…”

Section: Accessible Fpga Emulationmentioning

confidence: 99%

Vertically Integrated Computing Labs Using Open-Source Hardware Generators and Cloud-Hosted FPGAs

Amid

Asanović

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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The design of computing systems has changed dramatically over the past decade, but most courses in advanced computer architecture remain unchanged. Computer architecture education lies at the intersection between computer science and electrical engineering, with practical exercises in classes based on appropriate levels of abstraction in the computing system design stack. Hardware-centric lab exercises often require broad infrastructure resources and tend to navigate around tedious practical implementation concepts, while software-centric exercises leave a gap between modeling and system implementation implications that students later need to overcome in professional settings. Vertical integration trends in domain-specific compute systems, as well as software-hardware co-design, are often covered in classroom lectures, but are not reflected in laboratory exercises due to complex tooling and simulation infrastructure. We describe our experiences with a joint hardware-software approach to exploring computer architecture concepts in class exercises, by using opensource processor hardware implementations, generator-based hardware design methodologies, and cloud-hosted FPGAs. This approach further enables scaling course enrollment, remote learning and a cross-class collaborative lab ecosystem, creating a connecting thread between computer science and electrical engineering experience-based curricula.

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“…CoSA [41] 系统. 该系统基于 CoreIR 中间格式, 将所有对设计的分析问题转换为符号模型检验 [42] 问题, 基于限界模型检验技术 [43] 与 SMT 求解技术 [44] , 分别用 K-Induction [45] /Interpolation [46] 与 K-Liveness [47] 技术处理安全和活性性质的验证, 通过自动机乘利用 FPGA 或硬件云平台, 提升模拟效率 [50][51] . 代表性工作有加州大学伯克利分校的 RFUZZ 系统 [52] , 该系统将设计插桩后导入 FPGA, 提升模糊测试的性能.…”

Section: 形式化验证方面主要有针对敏捷设计方法的unclassified

Survey on Microprocessor Agile Design Methodology and Technology

Li¹,

Xu²,

Qu³

et al. 2021

J Comput-Aided Design Comput Graphics

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FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud

Cited by 11 publications

References 10 publications

An Open-Source Framework for FPGA Emulation of Analog/Mixed-Signal Integrated Circuit Designs

An Open-Source Framework for FPGA Emulation of Analog/Mixed-Signal Integrated Circuit Designs

Vertically Integrated Computing Labs Using Open-Source Hardware Generators and Cloud-Hosted FPGAs

Survey on Microprocessor Agile Design Methodology and Technology

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