Finite precision analysis of support vector machine classification in logarithmic number systems

Abstract

In this paper we present an analysis of the minimal hardware precision required to implement Support Vector Machine (SVM)

Boosting the Hardware-Efficiency of Cascade Support Vector Machines for Embedded Classification Applications

“…However, the iterative operations of these algorithms make it challenging to achieve high performance for applications that require high data throughput such as object detection, since compact implementations of CORDIC algorithms which require less hardware, have increased latency [32]. Other works [33], [34] proposed that the computations be done in the logarithmic number system so that all multiplications are substituted by additions, thus reducing computational resources. However, they only consider a single processing module, hence, when adopting a more parallel architecture, to facilitate real-time operation, the additional cost from converting between the decimal number system to the logarithmic one and back again for all inputs increases.…”

Generador automático de código que describe máquinas de soporte vectorial en hardware reconfigurable

“…Cada una requiere de dos bytes; una parte alta y otra baja debido a la representación Qn.m n+m=15 y al protocolo RS232 que envía bloques de 8 bits (figura 3.2(a)). Aquel tipo de representación fue utilizada debido a los resultados de [33,40]. Este sistema implementa el protocolo RS232 para lo que crea una instancia del puerto por medio de la biblioteca PSL de Celoxica DK 4.0.…”