Boosting the Hardware-Efficiency of Cascade Support Vector Machines for Embedded Classification Applications

Abstract

Support Vector Machines (SVMs) are considered as a state-of-the-art classification algorithm capable of high accuracy rates for a different range of applications. When arranged in a cascade structure, SVMs can efficiently handle problems where the majority of data belongs to one of the two classes, such as image object classification, and hence can provide speedups over monolithic (single) SVM classifiers. However, the SVM classification process is still computationally demanding due to the number of support vectors. Consequently, in this paper we propose a hardware architecture optimized for cascaded SVM processing to boost performance and hardware efficiency, along with a hardware reduction method in order to reduce the overheads from the implementation of additional stages in the cascade, leading to significant resource and power savings. The architecture was evaluated for the application of object detection on 800×600 resolution images on a Spartan 6 Industrial Video Processing FPGA platform achieving over 30 frames-per-second. Moreover, by utilizing the proposed hardware reduction method we were able to reduce the utilization of FPGA custom-logic resources by ~30%, and simultaneously observed ~20% peak power reduction compared to a baseline implementation.

FPGA Implementations of SVM Classifiers: A Review

“…Next, the previous work [69] is extended in [74,75], where a feature extraction mechanism (local binary pattern descriptors) is utilized within the proposed architecture to apply feature extraction before the final stage, aiming to enhance the detection accuracy. In [75], an additional novel response evaluation method is incorporated into the previously proposed architecture.…”

“…Most existing implementations target binary SVM classification (31 works), while only 12 works implement multiclass [69,73] Linear polynomial Face detection Xilinx ML505 (Virtex-5-LX110T) - [74] Linear polynomial Face and pedestrian detection Xilinx Spartan-6 XC6SLX150T - [75] Linear polynomial Face detection Xilinx Spartan-6 XC6SLX150T - [62,63] Linear classification and only one implements both [51]. This is probably because implementing a multiclass classifier is based on combining binary classifiers, and so numerous works focus on implementing the basic binary classifier to be then extended if required.…”

“…Moreover, only 14 existing implementations are developed by utilizing software system-design/development tools (category E), replacing the traditional design method using the HDL for decreasing FPGA development effort and time. The cascaded SVM classification (category F) is implemented on FPGA by only one research group [69,70,[72][73][74][75] (6 papers) that introduces heterogeneous architecture and hybrid architecture implemented using different techniques of categories A, C, and D. Recently, another research group [62,63] added a cascade SVM implementation in the literature based on a proposed multicore architecture using different hardware techniques of categories A, C and E.…”

“…In addition, some works have studied the quantization impact on the classification accuracy rate resulted from applying the fixed-point number formatting (bit-width precision) in the hardware implementation [23,27,28,32,44,74]. They aim to reduce hardware area while maintaining high accuracy.…”

“…Moreover, Afifi et al [60,61] have studied the trade-off between the speed/acceleration and hardware resources utilization/area with applying some different hardware architectures (HLS optimization directives), followed by similar analysis study focusing on design space exploration presented in [66,67]. As a result of applying different techniques for reducing hardware complexity and gaining acceleration, some implementations reported some loss in the classification accuracy rate [21,32,57,[67][68][69][73][74][75]. Furthermore, many works report classification speedup results compared to similar software implementations [23, 32, 35, 36, 54, 55, 57, 61-63, 66-68, 70, 72], and few works present a comparison with some related FPGA implementations in the literature [32, 60-63, 70, 72, 74, 75].…”