Dynamic hardware system for cascade SVM classification of melanoma

Abstract

Melanoma is the most dangerous form of skin cancer, which is responsible for the majority of skin cancer-related deaths. Early diagnosis of melanoma can significantly reduce mortality rates and treatment costs. Therefore, skin cancer specialists are using image-based diagnostic tools for detecting melanoma earlier. We aim to develop a handheld device featured with low cost and high performance to enhance early detection of melanoma at the primary healthcare. But, developing this device is very challenging due to the complicated computations required by the embedded diagnosis system. Thus, we aim to exploit the recent hardware technology in reconfigurable computing to achieve a high-performance embedded system at low cost. Support vector machine (SVM) is a common classifier that shows high accuracy for classifying melanoma within the diagnosis system and is considered as the most compute-intensive task in the system. In this paper, we propose a dynamic hardware system for implementing a cascade SVM classifier on FPGA for early melanoma detection. A multi-core architecture is proposed to implement a two-stage cascade classifier using two classifiers with accuracies of 98% and 73%. The hardware implementation results were optimized by using the dynamic partial reconfiguration technology, where very low resource utilization of 1% slices and power consumption of 1.5 W were achieved. Consequently, the implemented dynamic hardware system meets vital embedded system constraints of high performance and low cost, resource utilization, and power consumption, while achieving efficient classification with high accuracy.

FPGA Implementations of SVM Classifiers: A Review

“…The High-level Synthesis (HLS) design methodology has been recently used to decrease the FPGA development time and effort by using HLLs instead of HDLs. The Xilinx Vivado HLS tool [58] is exploited to implement a low-cost SVM IP [59][60][61][62][63][64] on a recent FPGA platform "Zynq SoC" with a hybrid architecture combining a processor with the FPGA in a single device [65]. An initial hardware/software co-design is implemented in [59] as an SVM accelerator to run the complicated processing task onto FPGA.…”

“…As a result of the simplified design, lower resources utilization and power consumption are demonstrated compared to a single SVM IP implementation, while enhancing the classification accuracy and speed (1.8 µs) as well as the diagnosis verification. Next, the hardware implementation results were optimized by using the powerful DPR technology (category C), where very low resource utilization of 1% slices and power consumption of 1.55 watts were achieved, while gaining flexibility, adaptability, scalability, and applicability [63]. The implemented SVM classification systems on Zynq SoC using the proposed hardware designs have shown the least power consumption results among other related implementations, in addition to significantly low hardware resource utilization and processing time with significant speedups and high classification accuracy rates at low cost.…”

“…Most existing implementations target binary SVM classification (31 works), while only 12 works implement multiclass [69,73] Linear polynomial Face detection Xilinx ML505 (Virtex-5-LX110T) - [74] Linear polynomial Face and pedestrian detection Xilinx Spartan-6 XC6SLX150T - [75] Linear polynomial Face detection Xilinx Spartan-6 XC6SLX150T - [62,63] Linear classification and only one implements both [51]. This is probably because implementing a multiclass classifier is based on combining binary classifiers, and so numerous works focus on implementing the basic binary classifier to be then extended if required.…”

Research and Implementation of ε-SVR Training Method Based on FPGA

“…Finally, the matrices A' and b are computed by the matrix A. For the design of storage mode of matrix A', this system refers to the methods in [19] and [20]. The results are stored in the external memory under the condition of large sample data, thereby saving on-chip resources.…”

“…It still requires a lot of manpower and time. In order to reduce the FPGA-based development cycle, Afifi et al implemented the SVM classifier for online detection of skin cancer based on Zynq platform, and the system power consumption is less than 1.5 W [19,20]. Hongda Wang et al proposed a real-time seizure detection hardware design based on STFT for nonlinear SVM [21].…”