FinFET SRAM with Enhanced Read / Write Margins

Balasubramanian

et al. 2010

IEEE Trans. VLSI Syst.

Abstract-Process-induced variations and sub-threshold leakage in bulk-Si technology limit the scaling of SRAM into sub-32 nm nodes. New device architectures are being considered to improve control and reduce short channel effects. Among the likely candidates, FinFETs are the most attractive option because of their good scalability and possibilities for further SRAM performance and yield enhancement through independent gating. The enhancements to read/write margins and yield are investigated in detail for two cell designs employing independently gated FinFETs. It is shown that FinFET-based 6-T SRAM cells designed with pass-gate feedback (PGFB) achieve significant improvements in the cell read stability without area penalty. The write-ability of the cell can be improved through the use of pull-up write gating (PUWG) with a separate write word line (WWL). The benefits of these two approaches are complementary and additive, allowing for simultaneous read and write yield enhancements when the PGFB and PUWG designs are used in combination.

Section: Device Architecturesmentioning

confidence: 99%

“…Just as feedback can be used to weaken the PG transistor during a read operation, it is possible to increase writeability by weakening the PU transistors during a write operation [31]. This can be achieved using independently gated FinFETs for the PU devices and connecting their BG to a write word line (WWL) (see Fig.…”

Section: ) Pull-up Write Gating (Puwg)mentioning

confidence: 99%

SRAM Read/Write Margin Enhancements Using FinFETs

Carlson

Balasubramanian

et al. 2010

IEEE Trans. VLSI Syst.

“…Margins such as write noise margin (WNM) and write N-curve require sweeping internal nodes in order to obtain the voltage transfer curves [9], [10]. We choose to characterize bit-line write trip voltage (BWTV) that can be measured by sweeping the bit-line voltages of the SRAM bitcell.…”

Section: Writeability 1) Static Writeability Marginsmentioning

confidence: 99%

Characterization of Dynamic SRAM Stability in 45 nm CMOS

Toh

IEEE J. Solid-State Circuits

Liu

et al. 2011

Abstract-Optimization of SRAM yield using dynamic stability metrics has been evaluated in the past to ensure continued scaling of bitcell size and supply voltage in future technology nodes. Various dynamic stability metrics have been proposed but they have not been used in practical failure analysis and compared with conventional static margins. This work compares static and dynamic metrics to identify expected correlations. A dynamic stability characterization architecture using pulsed word-lines is implemented in 45 nm CMOS to identify sources of variability, and their impact on SRAM stability. Static read margins were observed to overestimate failures by 10-100 X while static write margins failed to predict outliers in critical writeability. Critical writeability was demonstrated to exhibit an enhanced sensitivity to process variations, random telegraph noise (RTN), and negative bias temperature instability (NBTI), compared to static write margins.

“…The I write metric, derived from write N-curves [6] is used to characterize write margin fluctuation of the SRAM cells caused by RTS (Fig. 7-8).…”

Section: Impact Of Rts On Sram Write Marginmentioning

confidence: 99%

Impact of random telegraph signals on V<inf>min</inf> in 45nm SRAM

Toh

Tsukamoto

2009 IEEE International Electron Devices Meeting (IEDM)

et al. 2009

An alternating-bias random telegraph signal (RTS) characterization technique is presented, which shortens measurement time by 10x and also produces more accurate statistical distributions of RTS amplitudes. Measurements of RTS amplitudes in 45nm SRAM transistor I ds and cell write margin are reported and used to demonstrate a complex dependence of write margin on RTS in multiple transistors. Fail bit rate of SRAM with RTS is estimated using a statistical model populated by I write measurements. Statistical analysis indicates a V min degradation of less than 50 mV due to RTS.