FinFET SRAM hardening through design and technology parameters considering process variations

Villacorta, Hector; Champac, Victor; Bota, S.; Segura, J.

doi:10.1109/radecs.2013.6937372

Cited by 8 publications

(8 citation statements)

References 14 publications

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“…Although these devices may not cause incorrect behavior, they will lead to small delays or increased leakage current [3]. Furthermore, such devices may also cause reliability problems (e.g., shorter lifetime, higher failure rate) once used in field [21]. Therefore, detection of these devices is of great importance to assure high-quality and reliable FinFET devices.…”

Section: Finfet Srammentioning

confidence: 99%

“…Consequently, their detection is not guaranteed by approaches that use fault observation. Nevertheless, detection of such faults is of high importance as they may lead to test escapes and cause reliability problems (e.g., shorter lifetime, higher in-field failure rate) [21]. One approach to detect HTD faults is to introduce design-for-testability (DFT) circuitry into the memory to perform a special test (e.g., high-stress testing, parametric testing, etc.).…”

Section: Hard-to-detect Faultsmentioning

confidence: 99%

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A DFT Scheme to Improve Coverage of Hard-to-Detect Faults in FinFET SRAMs

Medeiros

Gürsoy

et al. 2020

2020 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Manufacturing defects can cause faults in FinFET SRAMs. Of them, easy-to-detect (ETD) faults always cause incorrect behavior, and therefore are easily detected by applying sequences of write and read operations. However, hard-to-detect (HTD) faults may not cause incorrect behavior, only parametric deviations. Detection of these faults is of major importance as they may lead to test escapes. This paper proposes a new designfor-testability (DFT) scheme for FinFET SRAMs to detect such faults by creating a mismatch in the sense amplifier (SA). This mismatch, combined with the defect in the cell, will incorrectly bias the SA and cause incorrect read outputs. Furthermore, postsilicon calibration schemes can be used to avoid over-testing or test escapes caused by process variation effects. Compared to the state of the art, this scheme introduces negligible overheads in area and test time while it significantly improves fault coverage and reduces the number of test escapes.

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Section: Finfet Srammentioning

confidence: 99%

Section: Hard-to-detect Faultsmentioning

confidence: 99%

A DFT Scheme to Improve Coverage of Hard-to-Detect Faults in FinFET SRAMs

Medeiros

Gürsoy

et al. 2020

2020 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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“…The study outcome shows enhancement in read / write stability in comparison to unstrained FinFET. Villacorta et al [34] have focused on reliability of SRAM using statistical approach. The summary of above discussion is tabulated below: [27] Buffer with read operation, 6T SRAM, 22 nm FinFET Better write ability, stabilized operation.…”

Section: Existing Techniquesmentioning

confidence: 99%

Insights of Performance Enhancement Techniques on FinFET-based SRAM Cells

Girish¹,

Shashikumar²

2016

CAE

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With the advancement in the energy efficient storage system, FinFET has already gained a pace in the area of computational memory management. However, after reviewing the research work focusing on FinFET based SRAM cells till date, we found that amount of research work towards enhancement of the design principle has not been much in number. Hence, we study some of the recently introduced research contribution towards enhancing the design performance of FinFET based SRAM cells and found that majority of the technique have both advantages and limitations too. We also highlights the significant research gap from the existing studies in order to assist the readers aware of the practicality of the research progress in this regards.

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“…Tests that rely on fault observation (e.g., March tests) can only detect RRFs that cause incorrect functional behavior. However, it is still essential to detect RRFs that do not lead to incorrect read outputs as they become test escapes, which are a known cause of no-troublefound devices [7] and in-field reliability issues [8]. Therefore, new high-quality methodologies to detect RRFs are essential to reduce test escapes and improve the quality and reliability of FinFET memories [9].…”

Section: Introductionmentioning

confidence: 99%

Detecting Random Read Faults to Reduce Test Escapes in FinFET SRAMs

Medeiros

Fieback

Gebregiorgis

et al. 2021

2021 IEEE European Test Symposium (ETS)

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Manufacturing defects in FinFET SRAMs can cause hard-to-detect faults such as Random Read Faults (RRFs). Detection of RRFs is not trivial, as they may not lead to incorrect outputs. Undetected RRFs become test escapes, which might lead to no-trouble-found devices and early in-field failures. Therefore, the detection of RRFs is of utmost importance. This paper proposes test solutions to detect RRFs and reduce test escapes. To achieve this, we first statistically analyze the failure rate due to RRFs, followed by an experimental study of stress conditions' (SCs) impact on detecting RRFs, such as test algorithms, supply voltage, and temperature. Based on the results, we propose a new Design-For-Testability (DFT) scheme for FinFET SRAMs to detect such faults using SCs that improve the detection rate of RRFs. This scheme introduces a negligible area and test time overhead while significantly enhancing RRF detection. Hence, using the proposed DFT leads to reduced test escapes and, consequently, higher-quality FinFET SRAMs.

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FinFET SRAM hardening through design and technology parameters considering process variations

Cited by 8 publications

References 14 publications

A DFT Scheme to Improve Coverage of Hard-to-Detect Faults in FinFET SRAMs

A DFT Scheme to Improve Coverage of Hard-to-Detect Faults in FinFET SRAMs

Insights of Performance Enhancement Techniques on FinFET-based SRAM Cells

Detecting Random Read Faults to Reduce Test Escapes in FinFET SRAMs

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