A DFT Scheme to Improve Coverage of Hard-to-Detect Faults in FinFET SRAMs

Medeiros, Guilherme Cardoso; Gürsoy, Cemil Cem; Wu, Lizhou; Fieback, Moritz; Jenihhin, Maksim; Taouil, Mottaqiallah; Hamdioui, Said

doi:10.23919/date48585.2020.9116278

Cited by 5 publications

(10 citation statements)

References 25 publications

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“…Weak-read test mode [22] applies voltage stress by creating a mismatch on the SA and biasing the amplification phase during a read operation. Thus, this kind of test fully covers random read functional HTD faults as it forces an incorrect behavior; other HTD faults are not targeted and therefore are not covered.…”

Section: B Previously Proposed Test Solutionsmentioning

confidence: 99%

“…Combining test solutions to improve overall coverage: as shown in Table VIII and Fig. 7, dedicated DFT circuits have been developed targeting HTD faults; some of them use the same SCs to detect different faults, e.g., voltage is used by the DFT circuit in [22] to detect random read faults, and in the DFT circuit in [20] to detect undefined state faults. Combining somewhat similar test solutions would increase the overall HTD faults coverage.…”

Section: Test Solutions Outlookmentioning

confidence: 99%

“…A solution to reduce test escapes is using Designfor-Testability (DFT) circuits and stress tests. Examples of DFT methodologies that can enhance HTD faults' detection are schemes that perform memory operations differently [20][21][22] or schemes that monitor some parameters of the memory [23][24][25]. Even though there are different test solutions, it is still unclear if they can efficiently cover HTD faults.…”

Section: Introductionmentioning

confidence: 99%

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Hard-to-Detect Fault Analysis in FinFET SRAMs

Medeiros

Fieback

et al. 2021

IEEE Trans. VLSI Syst.

Self Cite

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Manufacturing defects can cause Hard-to-Detect (HTD) faults in FinFET SRAMs. Detection of these faults, such as random read outputs and out-of-spec parametric deviations, is essential when testing FinFET SRAMs. Undetected HTD faults result in test escapes, which lead to early in-field failures. This paper presents a detailed analysis of HTD faults in FinFET SRAMs by exploring their sensitization and discussing solutions to improve HTD fault coverage during manufacturing testing. We first define the fault space for SRAMs and classify all faults in the space. Following this, we perform a systematic fault analysis based on injecting resistive defects in a memory cell, inspecting its behavior, and identifying HTD faults. Furthermore, we survey existing test solutions and discuss their HTD fault coverage and limitations. Based on our analysis, it is clear that no single test solution can fully detect all HTD faults, thus leading to test escapes. Hence, there is a need for new and more efficient test solutions. Improved detection of HTD faults could be achieved by using parametric test solutions, proposing solutions that cover yet-untargeted HTD faults, combining multiple test approaches into a single solution, and further exploring stress conditions. These new approaches would reduce test escapes and therefore improve the quality of FinFET SRAMs.

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Section: B Previously Proposed Test Solutionsmentioning

confidence: 99%

Section: Test Solutions Outlookmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Hard-to-Detect Fault Analysis in FinFET SRAMs

Medeiros

Fieback

et al. 2021

IEEE Trans. VLSI Syst.

Self Cite

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“…Hence, efficient techniques for production testing and for periodic maintenance testing are mandatory to guarantee the required quality standards. However, advances in memory technology and system design have turned memory testing into a nontrivial task [ 2 , 3 , 4 ]. The complexity of the memory chips makes fault modeling and testing an evermore challenging problem.…”

Section: Introductionmentioning

confidence: 99%

Transparent Memory Tests Based on the Double Address Sequences

Mrozek

Yarmolik

2021

Entropy

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An important achievement in the functional diagnostics of memory devices is the development and application of so-called transparent testing methods. This is especially important for modern computer systems, such as embedded systems, systems and networks on chips, on-board computer applications, network servers, and automated control systems that require periodic testing of their components. This article analyzes the effectiveness of existing transparent tests based on the use of the properties of data stored in the memory, such as changing data and their symmetry. As a new approach for constructing transparent tests, we propose to use modified address sequences with duplicate addresses to reduce the time complexity of tests and increase their diagnostic abilities.

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“…Therefore, more complex test solutions (e.g., more extreme stressing conditions and Design-for-Testability (DFT) circuits) must be used when targeting RRFs. Examples of such test solutions are schemes that change how read operations are executed [13][14][15], and schemes that monitor memory parameters [16][17][18]. However, both approaches have limitations; the former may over-test the memory due to inappropriate stresses, thus leading to yield loss, while the latter may be negatively impacted by process variation (PV) effects, thus leading to test escapes.…”

Section: Introductionmentioning

confidence: 99%

Detecting Random Read Faults to Reduce Test Escapes in FinFET SRAMs

Medeiros

Fieback

Gebregiorgis

et al. 2021

2021 IEEE European Test Symposium (ETS)

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Manufacturing defects in FinFET SRAMs can cause hard-to-detect faults such as Random Read Faults (RRFs). Detection of RRFs is not trivial, as they may not lead to incorrect outputs. Undetected RRFs become test escapes, which might lead to no-trouble-found devices and early in-field failures. Therefore, the detection of RRFs is of utmost importance. This paper proposes test solutions to detect RRFs and reduce test escapes. To achieve this, we first statistically analyze the failure rate due to RRFs, followed by an experimental study of stress conditions' (SCs) impact on detecting RRFs, such as test algorithms, supply voltage, and temperature. Based on the results, we propose a new Design-For-Testability (DFT) scheme for FinFET SRAMs to detect such faults using SCs that improve the detection rate of RRFs. This scheme introduces a negligible area and test time overhead while significantly enhancing RRF detection. Hence, using the proposed DFT leads to reduced test escapes and, consequently, higher-quality FinFET SRAMs.

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A DFT Scheme to Improve Coverage of Hard-to-Detect Faults in FinFET SRAMs

Cited by 5 publications

References 25 publications

Hard-to-Detect Fault Analysis in FinFET SRAMs

Hard-to-Detect Fault Analysis in FinFET SRAMs

Transparent Memory Tests Based on the Double Address Sequences

Detecting Random Read Faults to Reduce Test Escapes in FinFET SRAMs

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