Fine-Grain Redundant Logic Using Defect-Prediction Flip-Flops

Abstract

and prevents failures before defects actually cause errors, thereby our circuit maintains correct operations using both time and NEC, Kanagawa, Japan circuit redundancy.As CMOS process technology advances, an initial failure compen-As shown in Fig. 22.3.4, DPFFs with MUX-scan are 3.15x larger sation technique for yield enhancement, and an in-field failure than normal DFFs with MUX-scan, and the combination-logic prevention technique against increasing in-field failure rates are area for a FGR design is more than twice as large due to its becoming crucial, especially in such highly-dependable chip marredundancy and warning distribution OR gates. If the area ratio ket as automotive. This paper introduces fine-grain redundant of combination-logic/DFF is 6:4, the area becomes about 2.5x logic (FGR) for switching only a defective portion of a main circuit larger. Considering, however, the ITRS prediction that the area having killer/latent defects to its redundant sub-circuit block, and ratio on an SoC for logic/memory will reduce, as the process techdefect prediction flip-flops (DPFFs) for the autonomous predicnology advances to 12/88 at a 45nm node, for example, the overtion and prevention of in-field failures due to latent defects, as all area penalty is only 18%, as shown in Fig. 22.3.4. A chip yield, shown in Fig. 22.3.1. Rere, killer defects refer to those apparent with respect to the logic area of, for example, 70% would increase at fabrication process, while latent defects refer to those apparent to 91% under the assumption that a) FGR designs have more only in actual use. While redundant circuits to compensate than 1000 grains within a logic area being increased by 2.5x and defect-related multi-failures have been widely used for memory, b) 10% of defects are related to DPFFs which do not have redunwe introduce redundancy into logic circuits as well. The DPFFs dancy. This number 10% is arrived at assuming that DPFFs occuare connected via the scan chain through which defect points are py 50% of the logic area and that the portion of defects occurring traced. The scan chain is connected to an external nonvolatile under the Ml layer in a multi-metal layer process is 20% memory so as to reproduce main or sub switching states on the (0.5x0.2=0.1). Furthermore, more than 80% in-field failures due basis of screening tests and in-field failure prevention results. to two latent defects are prevented, while a triplicate scheme Our estimates show that the application of this scheme enhances with a winner-take-all circuit would prevent only 33%, and single a production yield of, for example, 70% to 91% even with considand duplicate schemes would prevent none, as shown in Fig. ering the area increase due to the redundancy, and it prevents 22.3.4. These yield enhancement and in-field failure reductions over 80% of in-field failures caused by one or two latent defects on prevail over the disadvantage of the chip area increase. a chip. To evaluate our scheme, we first design and fabricate failure pre-Chips with latent defects ...

A Scan-Based On-Line Aging Monitoring Scheme

“…All of the cells basically include a flip-flop (or latch) and an XOR gate as shown in the Additional Logic column. In order to capture delayed data, Canary FF [11], Aging Sensor FF [12], and DPFF [13] put a delay element on the data path, but Razor FF [10] and Aging Aware FF [14] used a delayed clock instead of generating delay on data path which create a relatively large area for additional clock tree or clock delay circuit. Although the proposed ECSC has 2 MUXs and uses a duty cycle adjustable clock, it has relatively less overhead in a large design because no data/clock delay circuit and additional clock tree are needed.…”

“…Each of them uses two flip-flops (or a flip-flop and a latch), one to capture the normal data and the other one to capture the delayed data, and checks if timing constraints are met. In order to capture the delayed data, Razor flip-flop [10] and Aging Aware FF [14] use a delayed clock and the others [11][12][13] put a delay element. Therefore, the area overhead due to the delayed clock circuits or the delay elements is very high.…”

Adaptive performance compensation with on-chip variation monitoring

“…However, its efficiency is deteriorating because the performance mismatch between the replica and the actual critical path tends to be significant due to increasing within-die variation and aging. To more efficiently sense the timing margin, in-situ techniques have been studied [9]- [12]. Nevertheless, this scheme inherently involves a critical risk of timing error occurrence.…”

“…In contrast, "Canary Flip-Flop" [11] and "Defect Prediction Flip-Flop (DPFF)" [12] have been proposed that aim not to detect timing errors but to predict them. When the timing margin is not enough, they capture wrong values, whereas the main flip-flops capture correct values.…”

An On-Chip Test Clock Control Scheme for Circuit Aging Monitoring

“…Agarwal et al [6,7] and T. Nakura et al [8] designed aging sensors checking whether the signal transition of the combinational logic output occurs out of the guard-band time interval. These techniques enable aging to be observed concurrently during normal operation by directly checking aging of actual data paths during normal operation.…”