Finding fault with deep-submicron ICs

Time-resolved optical characterization of electrical activity in integrated circuits

“…This geometry is shown in Fig. 1 [3]. In a "flip-chip" package, the backside of the Si substrate is "over" the front side, severely constraining physical access to the FETs and wiring.…”

“…The need for "at-speed" gate-level test and diagnostics in contemporary ICs has been surveyed in two recent IEEE Spectrum articles [3], [9]. Vallett and Soden [3] discuss approaches where the electrical waveforms in circuits are measured.…”

“…Vallett and Soden [3] discuss approaches where the electrical waveforms in circuits are measured. This can be done through metallic probes, which physically contact metal lines to measure their voltages.…”

“…1. Schematic of the cross section of a modern silicon integrated circuit showing multiple layers of metallization, solder balls for flip-chip packaging, and defining the front and back sides of the chip [3].…”

“…Failure to develop physical analysis tools matched to the new aspects of advanced chips can threaten the successful introduction of these ICs [3]. New features include the increasing number of wiring layers, growing importance of in-terconnects and timing failures in limiting high-speed performance, use of flip-chip packaging, ever smaller device sizes, and use of internal clock speeds exceeding the input-output (I/O) bandwidths.…”