Finding best voltage and frequency to shorten power-constrained test time

Abstract

Abstract-In a digital test, supply voltage (VDD), clock frequency (ftest), peak power (PMAX ) and test time (T T ) are related parameters. For a given limit PMAX = PMAXfunc, normally set by functional specification, we find the optimum VDD = VDDopt and ftest = fopt to minimize T T . A solution is derived analytically from the technology-dependent characterization of semiconductor devices. It is shown that at VDDopt the peak power any test cycle consumes just equals PMAXfunc and ftest is fastest that the critical path at VDDopt will allow. The paper demonstrates how test parameters can be obtained numerically from MATLAB, or experimentally by bench test equipment like National Instruments' ELVIS. This optimization can cut the test time of ISCAS'89 benchmarks in 180nm CMOS into half.

A Test Time Theorem and its Applications

“…For all lower voltages the minimum test time increases with T structure . Table I shows the results of optimized test obtained by an analytical procedure [11]. These results have been verified by Spice simulation [10].…”

“…Simulation results have shown the feasibility of this idea [9], [8]. Recent papers show that voltage reduction can increase the speed of power constrained synchronous testing [10], [11].…”

“…In this case, P AV = P P EAKf unc . Both limiting cases are according to Equation (11). The minimum test time for an asynchronous test is sketched in Figure 2 for varying supply voltages.…”

ATE test time reduction using asynchronous clock period

“…Some authors [7], [9] propose methods that can overcome this problem while achieving similar test time reduction as in multiple scan chains. Recent papers [31], [34] find an optimum voltage that is used in scan test for stuck at faults to improve test time in power constrained circuits without violating any timing constraints at reduced voltage, while considering the power dissipated in both shift and capture cycles. Test time reduction for multicore SoC designs requires power-constrained scheduling of tests [13], [19].…”

“…The proposed method is then verified first through simulation and then experimentally on an Advantest T2000GS ATE. Although the research as it appears here has never been presented in entirety, parts have been displayed as posters [30], [32] or discussed at technical forums [5], [6], [31], [33], [34].…”