Finding all elementary circuits exploiting transconductance

Klumperink, Eric A.M.; Bruccoleri, F.; Nauta, Bram

doi:10.1109/82.982356

Cited by 27 publications

(14 citation statements)

References 8 publications

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“…The topological properties of a VCCS can be represented by a graph with a v and i branch. (b) All potentially useful graphs of two-port circuits with 2VCCS have been generated (i.e., the 2VCCS graph database) [6], [7]. Fig.…”

Section: The Systematic Approachmentioning

confidence: 99%

Generating all two-MOS-transistor amplifiers leads to new wide-band LNAs

Bruccoleri

Klumperink

Nauta

2001

IEEE J. Solid-State Circuits

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Abstract-This paper presents a methodology that systematically generates all 2-MOS-transistor wide-band amplifiers, assuming that a MOSFET is exploited as a voltage-controlled current source (VCCS). This leads to new circuits. Their gain and noise factor have been compared to well-known wide-band amplifiers. One of the new circuits appears to have a relatively low noise factor, which is also gain independent. Based on this new circuit, a 50-900 MHz variable-gain wide-band low noise amplifier (LNA) has been designed in 0.35-m CMOS. Measurements show a noise figure between 4.3 and 4.9 dB for gains from 6 to 11 dB. These values are more than 2 dB lower than the noise figure of the wide-band common-gate LNA for the same input matching, power consumption, and voltage gain. IIP2 and IIP3 are better than 23.5 and 14.5 dBm, respectively, while the LNA drains only 1.5 mA at 3.3 V.

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Section: The Systematic Approachmentioning

confidence: 99%

Generating all two-MOS-transistor amplifiers leads to new wide-band LNAs

Bruccoleri

Klumperink

Nauta

2001

IEEE J. Solid-State Circuits

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“…This was primarily done with brute-force like approaches by Klumperink et al [KBN01,BKN00]. Remarkably, this approach has an explorative nature, which is maybe the first of its kind.…”

Section: State-of-the-art In Analog Synthesismentioning

confidence: 99%

“…Library-based [MCR95] Klumperink [KBN01] Geometric Prog. [dMH04] First evolutionary [KL95] FEATS Hierarchical evolutionary [MPSG09] Advanced evolutionary [AII03] Guided [SKP05] By hand Bell number…”

Section: Expert-knowledgementioning

confidence: 99%

FEATS: Framework for Explorative Analog Topology Synthesis

Meißner

Hedrich

2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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The presented work inside this thesis aims to raise the degree of automation in analog circuit design. Therefore, a framework was developed to provide the necessary mechanisms in order to carry out a fully automated analog circuit synthesis, i.e., the construction of an analog circuit fulfilling all previously defined (electrical) specifications.Nowadays, analog circuit design in general is a very time consuming process compared to a digital design flow. Due to its discrete nature, the digital design process is highly automated and thus very efficient compared to analog circuit design. In modern Very-Large-Scale integration (VLSI) circuits the analog parts are mostly just a small portion of the overall chip area. Although this small portion is known to consume a major part of the needed workforce. Paired with product cycles which constantly get shorter, the time needed to develop the analog parts of an integrated circuit (IC) becomes a determinant factor. Apart from this, the ongoing progress in semiconductor processing technologies promises more speed with less power consumption on smaller areas, forcing the IC developers to keep track with the technology nodes in order to maintain competitiveness. Analog circuitry exhibits the inherent property of being hard to reuse, as porting from one technology node to another imposes critical changes for operating conditions (e.g., supply voltage) -mostly leading to a full redesign for most of the analog modules. This productivity gap between digital and analog design resembles the primary motivation for this thesis.Due to the availability of commercial sizing tools, this work deliberately focuses on the construction of circuit topologies in distinction to parameter synthesis, which can be obtained with a dedicated sizing tool. The focus on circuit construction allows the development of a framework which allows a full design space exploration. This thesis describes the needed concepts and methods to realize a deterministic, explorative analog synthesis framework. Despite this, a reference implementation is presented, which demonstrates the applicability in current analog design flows. circuit (c) a circuit representing a physical realization circuits (C) an unordered set of circuits design space (DS) design space seen as crossproduct of P S and ST S devices (M ) an unordered set of devices equivalence class (eqcls) an unordered set of objects sharing the combination set of invariant properties equivalence classes (EQCLS(c)) set of equivalence classes associated with the circuit c graph (G) a representation of object vertices connected through edges ground (V GN D ) name of the reference net or simply ground hash (hash(x)) hash associated with object x integer (N) integer numbers invariant properties (EQP ROP S(x)) set of invariant properties associated with x invariant property (p) a property associated with a specific IV i invariants (IV) an unordered set of invariants label (L(x)) label associated with object x nets (N ) an unordered set of nets parameter space ...

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“…However EDA tools for analog circuits are still not mature compared to those for digital circuits [3]. By now a lot of papers present different structural synthesis methods using knowledge-based approaches [4], full exploration techniques [5] or genetic algorithm [6]. Most of them are applied in generating circuits with linear functions e.g.…”

Section: Introductionmentioning

confidence: 99%