FEATS: Framework for Explorative Analog Topology Synthesis

Abstract

The presented work inside this thesis aims to raise the degree of automation in analog circuit design. Therefore, a framework was developed to provide the necessary mechanisms in order to carry out a fully automated analog circuit synthesis, i.e., the construction of an analog circuit fulfilling all previously defined (electrical) specifications.Nowadays, analog circuit design in general is a very time consuming process compared to a digital design flow. Due to its discrete nature, the digital design process is highly automated and thus very efficient compared to analog circuit design. In modern Very-Large-Scale integration (VLSI) circuits the analog parts are mostly just a small portion of the overall chip area. Although this small portion is known to consume a major part of the needed workforce. Paired with product cycles which constantly get shorter, the time needed to develop the analog parts of an integrated circuit (IC) becomes a determinant factor. Apart from this, the ongoing progress in semiconductor processing technologies promises more speed with less power consumption on smaller areas, forcing the IC developers to keep track with the technology nodes in order to maintain competitiveness. Analog circuitry exhibits the inherent property of being hard to reuse, as porting from one technology node to another imposes critical changes for operating conditions (e.g., supply voltage) -mostly leading to a full redesign for most of the analog modules. This productivity gap between digital and analog design resembles the primary motivation for this thesis.Due to the availability of commercial sizing tools, this work deliberately focuses on the construction of circuit topologies in distinction to parameter synthesis, which can be obtained with a dedicated sizing tool. The focus on circuit construction allows the development of a framework which allows a full design space exploration. This thesis describes the needed concepts and methods to realize a deterministic, explorative analog synthesis framework. Despite this, a reference implementation is presented, which demonstrates the applicability in current analog design flows. circuit (c) a circuit representing a physical realization circuits (C) an unordered set of circuits design space (DS) design space seen as crossproduct of P S and ST S devices (M ) an unordered set of devices equivalence class (eqcls) an unordered set of objects sharing the combination set of invariant properties equivalence classes (EQCLS(c)) set of equivalence classes associated with the circuit c graph (G) a representation of object vertices connected through edges ground (V GN D ) name of the reference net or simply ground hash (hash(x)) hash associated with object x integer (N) integer numbers invariant properties (EQP ROP S(x)) set of invariant properties associated with x invariant property (p) a property associated with a specific IV i invariants (IV) an unordered set of invariants label (L(x)) label associated with object x nets (N ) an unordered set of nets parameter space ...

FUBOCO: Structure Synthesis of Basic Op-Amps by FUnctional BlOck COmposition

“…As an experienced designer can do this selection instantly, there is little gain in design time or design quality. The other path of structural synthesis builds up the netlist by combining modules of transistors and transistor groups while satisfying Kirchhof laws and basic voltage/current conversion at the module interfaces [12,16,20,28,36,37,56]. Here, a plethora of variants is created, from which the promising ones are selected only after symbolic analysis and complete sizing.…”

“…To size the topologies and evaluate their practicability, simulations are used. To lessen the number of redundant op-amp topologies, graph-grammar based approaches were developed [12,37,56]. With strict grammar rules and isomorphism techniques, the number of redundant topologies are reduced.…”

“…But it is still close enough to the op-amp structure such that redundant or impracticable topologies are avoided. Thus, algorithms to remove these structures as in [37,56] are unnecessary in this new approach. A novel algorithm for structural synthesis iteratively composes op-amp netlists from these basic functional blocks.…”

“…The state-of-the-art synthesis [24] 70 Topology selection from library with subblock templates < 0.2 h Equation-based Gerlach [21] 24 Topology selection from library < 0.5 h Numerical Koza [28] > 10 000 Genetic algorithm based on library with devices w/ or w/o self-connections 2 d Numerical MOJITO-R [36] 3500 Genetic algorithm based on library with devices w/ or w/o self-connections 15 h Numerical Das [12] > 10 000 Graph algorithm on library with devices w/ or w/o self-connections N.a. Numerical Feats [37] > 10 000 Graph algorithm on basic building blocks library 8 h Numerical Zhao [56] 4000 approaches based on equation-based methods to evaluate circuit topologies, e.g., [24,35], use a topology selection method to decide for a topology. This is diferent in this method as the topology independent sizing process presented in detail in [7] allows the synthesis and evaluation of thousands of diferent topologies, as the set-up of the equation-based description is automated.…”

An Automatic Circuit Design Framework for Level Shifter Circuits

“…Buildingblock-based methods [7]- [9] take a similar approach, but rely on a library of smaller building blocks such as a current mirror and a differential input pair. They employ various algorithms to search for the best topology, such as multiobjective evolutionary algorithm [7], framework for explorative analog topology synthesis method (FEATS) [8], and graph-grammar-based topology generation (GGTG) [9]. Since the library-or building-block-based approaches have relatively limited search space, they are suitable for the fast generation of integrated circuits using a well-established topology.…”