Fin bending mechanism investigation for 14nm FinFET technology

Li, Cheng; Zhao, Hai; Mao, Gang

doi:10.1109/cstic.2017.7919800

Cited by 3 publications

(3 citation statements)

References 2 publications

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“…2 The non-uniformities can reduce the performance of the device; the leakage current may increase, and it also affects the CMOS threshold voltage. 2,3 For these transistors to work as efficiently as possible, it is particularly important to monitor the complex, multi-step processes, and reveal the possible imperfections. With the appearance of new devices, new types of defects also arise, which require new metrological solutions.…”

Section: Introductionmentioning

confidence: 99%

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Detection of structural asymmetries in Forksheet FET arrays using Mueller matrix ellipsometry: a theoretical study

Dikó,

Kiss,

Egri

et al. 2024

J. Micro/Nanopattern. Mats. Metro.

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Background: With the appearance of ever-smaller transistors and new structures, new metrological challenges also arise, including the detection of different structural defects. Mueller matrix (MM) measurement can provide an opportunity to investigate them.Aim: Defects can cause a deterioration in device performance; therefore, their characterization is particularly important. Our goal is to investigate the possibility of detecting asymmetry defects using MM measurement and to study the distinguishability of these structural imperfections in the case of forksheet field-effect transistor (FET).Approach: Simulation of MM measurements with different degrees and directions of forksheet FET's profile asymmetries. To quantify the distinguishability of the optical responses caused by the defects, the correlation between the asymmetry parameters was calculated. Since the precise alignment of a sample is a key factor in the detection of asymmetries, the effect of the alignment uncertainty and a method for filtering it out were also investigated.Results and Conclusions: MM measurement is sensitive to both the magnitude and direction of the profile bending and the shift of the dielectric wall. The correlation coefficients show that the optical responses of the asymmetry defects and the alignment error can be distinguished. The latter can even be eliminated with a method presented in this article.

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Section: Introductionmentioning

confidence: 99%

“…However, the dimension of the defects that may occur in the structures does not change, so their effect becomes increasingly significant 2 . The non-uniformities can reduce the performance of the device; the leakage current may increase, and it also affects the CMOS threshold voltage 2 , 3 …”

Section: Introductionmentioning

confidence: 99%

Detection of structural asymmetries in Forksheet FET arrays using Mueller matrix ellipsometry: a theoretical study

Dikó,

Kiss,

Egri

et al. 2024

J. Micro/Nanopattern. Mats. Metro.

View full text Add to dashboard Cite

show abstract

“…Its leaning angle forms an asymmetric depletion area and makes the leakage current larger than expected. (8) On the other hand, tensile and compressive stresses, which are two components of mechanical stress, will respectively improve electron and hole mobilities. (9,10) Stresses are intentionally introduced into the device channel by means of a silicon-carbon (SiC) source and drain (S/D), a strained cap layer, shallow trench insulation (STI), and so forth during the transistor fabrication process.…”

Section: Introductionmentioning

confidence: 99%

Impact of Active Surface Area on Performance and Reliability of Tri-gate FinFET

Yang

Chuang

Lai

et al. 2019

Sensors and Materials

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In this work, a contact etch stop layer (CESL) was found to cause tensile stress above the gate of FinFET devices, and the top tensile stress introduced compressive stress in the channel. With increasing active surface area (SA), a higher compressive stress was observed. The effect of compressive stress became more evident, resulting in a lower current but a higher reliability for nFinFET devices.

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Simulation Study: The Impact of Structural Variations on the Characteristics of a Buried-Channel-Array Transistor (BCAT) in DRAM

2022

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As the physical dimensions of cell transistors in dynamic random-access memory (DRAM) have been aggressively scaled down, buried-channel-array transistors (BCATs) have been adopted in industry to suppress short channel effects and to achieve a better performance. In very aggressively scaled-down BCATs, the impact of structural variations on the electrical characteristics can be more significant than expected. Using a technology computer-aided design (TCAD) tool, the structural variations in BCAT (e.g., the aspect ratio of the BCAT recess-to-gate length, BCAT depth, junction depth, fin width, and fin fillet radius) were simulated to enable a quantitative understanding of its impact on the device characteristics, such as the input/output characteristics, threshold voltage, subthreshold swing, on-/off-current ratio, and drain-induced barrier lowering. This work paves the road for the design of a variation-robust BCAT.

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Fin bending mechanism investigation for 14nm FinFET technology

Cited by 3 publications

References 2 publications

Detection of structural asymmetries in Forksheet FET arrays using Mueller matrix ellipsometry: a theoretical study

Detection of structural asymmetries in Forksheet FET arrays using Mueller matrix ellipsometry: a theoretical study

Impact of Active Surface Area on Performance and Reliability of Tri-gate FinFET

Simulation Study: The Impact of Structural Variations on the Characteristics of a Buried-Channel-Array Transistor (BCAT) in DRAM

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