Filament scaling forming technique and level-verify-write scheme with endurance over 107 cycles in ReRAM

Kawahara, Akifumi; Kawai, K.; Ikeda, Y.; Katoh, Y.; Azuma, R.; Yoshimoto, Yuma; Tanabe, K.; Wei, Zhiqiang; Ninomiya, T.; Kawasaki, Koji; Yasuhara, Ryo; Muraoka, S.; Himeno, A.; Yoshikawa, Naoki; Murase, Hideaki; Shimakawa, K.; Takagi, Toshihisa; Mikawa, Takumi; Aono, K.

doi:10.1109/isscc.2013.6487708

Cited by 35 publications

(21 citation statements)

References 5 publications

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“…However, the precondition of the approximation may be difficult to be satisfied and may decrease computation accuracy. For example, R ON ≈ 1kΩ for a physical RRAM device [11], [18] and N l=1 c k,l ≈ 5 for a 256 × 256 RRAM crossbar array [7]. And according to Eq.…”

Section: The Third Stage: Map Matrix Parameters To Rram Device Conmentioning

confidence: 99%

Technological exploration of RRAM crossbar array for matrix-vector multiplication

Tang

et al. 2015

The 20th Asia and South Pacific Design Automation Conference

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The matrix-vector multiplication is the key operation for many computationally intensive algorithms. In recent years, the emerging metal oxide resistive switching random access memory (RRAM) device and RRAM crossbar array have demonstrated a promising hardware realization of the analog matrix-vector multiplication with ultra-high energy efficiency. In this paper, we analyze the impact of nonlinear voltage-current relationship of RRAM devices and the interconnect resistance as well as other crossbar array parameters on the circuit performance and present a design guide. On top of that, we propose a technological exploration flow for device parameter configuration to overcome the impact of nonideal factors and achieve a better trade-off among performance, energy and reliability for each specific application. The simulation results of a support vector machine (SVM) and MNIST pattern recognition dataset show that the RRAM crossbar array-based SVM is robust to the input signal fluctuation but sensitive to the tunneling gap deviation. A further resistance resolution test presents that a 4bit RRAM device is able to realize a recognition accuracy of ∼ 90%, indicating the physical feasibility of RRAM crossbar array-based SVM. In addition, the proposed technological exploration flow is able to achieve 10.98% improvement of recognition accuracy on the MNIST dataset and 26.4% energy savings compared with previous work.

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Section: The Third Stage: Map Matrix Parameters To Rram Device Conmentioning

confidence: 99%

Technological exploration of RRAM crossbar array for matrix-vector multiplication

Tang

et al. 2015

The 20th Asia and South Pacific Design Automation Conference

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“…Similarly, ReRAM has the reliability issues of the resistive switching. Previous work [6] implemented the recovery algorithm into write operations due to the measure of abnormal bit behavior. Thus reliability issues for emerging memories are still remained and might hamper the switching current reduction and the memory cell shrinkage.…”

Section: Toward the Emerging Memoriesmentioning

confidence: 99%

Prospect of embedded non-volatile memory in the smart society

Yamauchi

2015

2015 International Symposium on VLSI Technology, Systems and Applications

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Embedded Flash (eFlash) is widely accepted by various applications because of reducing overall costs of system development, production and inventory. Continuous evolution of eFlash such as the split-gate charge-trapping memory has satisfied the most stringent quality requirement for automotive applications. Smart society for offering a better quality of life would diversify NV memory until the establishment of emerging memories. Add-on type eFlash with a few additional masks would replace the stand-alone data flash for adaptive tuning and security over the network. Towards the possible convergence of NV-memory in smart society, emerging memories such as ReRAM and STT-MRAM are progressing. Excellent features of smaller rewrite energy with the extending rewrite cycles could contribute to the outstanding energy saving such as normally-off systems.

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“…Among all others Back-Endof-Line (BEoL) resistive memory candidates (e.g. Phase Change or Magnetic Memory -PCM, MRAM), Oxide-based and Conductive bridge-based RRAM (OxRAM, CBRAM) are the most promising since their Metal-Insulator-Metal (MIM) structure is composed of materials already available in foundries, thereby driving down the process costs [2] [3]. However, while bipolar behavior (featured by most of the 2terminals OxRAM, CBRAM or MRAM technologies) enables better endurance and lower energy consumption [4] than unipolar device, new constraints appear if co-integrated with unipolar selectors such as Metal Oxide Semiconductor (MOS) transistors.…”

Section: Introductionmentioning

confidence: 99%

Resistive Switching Memory Architecture Based on Polarity Controllable Selectors

Levisse

Gaillardon

Giraud

et al. 2019

IEEE Trans. Nanotechnology

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With the continuous scaling of CMOS technology, integrating an embedded high-density non-volatile memory appears to be more and more costly and technologically challenging. Beyond floating-gate memory technologies, bipolar Resistive Random Access Memories (RRAM) appear to be one of the most promising technologies. However, when organized in a 1 or 2-Transistor 1-RRAM (1T1R, 2T1R) architectures, they suffer from large bitcell area, degraded performance and reliability issue during reset operation. The association of multiple-independentgate Polarity Controllable Transistors (PCT) with RRAM overcomes these drawbacks, while providing a dense structure. In this paper, we present two innovative PCT-based bitcells and propose an extensive study of their functionality, physical design considerations and performances in read and write operations compared to CMOS-based 1T1R and 2T1R bitcells. The proposed bitcells outperform the performances of 1T1R and 2T1R bitcells in reset (5× to 105× speed improvement) are competitive in term of area (1.35× to 2.6× area reduction versus 2T1R) and avoid gate overdrive (1.2V versus more than 2V in 1T1R bitcells) thus reducing selector reliability concerns. We also propose an innovative programming strategy which takes advantage of the PCT polarity control and enabling 500× improvement in reset performance. Finally, the proposed bitcells performs 15 to 67% faster than CMOS bitcells in read.

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Filament scaling forming technique and level-verify-write scheme with endurance over 107 cycles in ReRAM

Cited by 35 publications

References 5 publications

Technological exploration of RRAM crossbar array for matrix-vector multiplication

Technological exploration of RRAM crossbar array for matrix-vector multiplication

Prospect of embedded non-volatile memory in the smart society

Resistive Switching Memory Architecture Based on Polarity Controllable Selectors

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