Field Programmable Gate Arrays Based Overcurrent Relays

Abstract

This paper presents a novel technique of implementing overcurrent relays on field programmable gate arrays (FPGA), which can be used for the protection of distribution lines, large industrial motors and many equipments of the power system. Due to its reconfigurability, it gives an idea to implement many types of relays on the single FPGA board. In case of microprocessor based relays, many peripheral devices are required making the operation slower; but in the case of FPGA, the same can be realized with less number of peripherals, thus making the operation faster. The proposed overcurrent relay gives satisfactory results when simulated on the Xilinx FPGA, thus providing the best solution in the existing technologies.

Development of a novel single chip solution for a motor protection relay

“…By implementing the Filter on same chip, as opposed to [5], the cost of using external filter is saved. Also, the reconfigurability and insystem programmability of FPGA provides the option of producing the most optimal design for any application [9].…”

“…The earlier relay prototypes developed, as in [5], have used VHDL for developing the source code. In the present work-Verilog Hardware Description language has been used to develop the simulation model of relays.…”

“…The protective relaying [4], [5], [2] which responds to a rise in current flowing through the protected element over a predetermined value is called 'over-current protection' and the relays used for this purpose are known as over-current relays. The algorithm used to build the over-current relay is presented below:…”

“…A number of designs have been discussed in the literature for implementing protective relays on FPGA. [3], [4], [5] discuss the implementation of various current relays on FPGA. [6] discusses the voltage and frequency relays being implemented on FPGA chip.…”

Prototyping and hardware‐in‐loop verification of OCR

“…This hardware design requires allocation of the huge amount of hardware resources. Another FPGA-based inverse definite minimum time OCR is reported in [13]. In [14], a system on programmable chip-based OCR design is presented.…”